Aaron Spink (aaronspink.delete@this.notearthlink.net) on January 24, 2017 6:44 am wrote:
> vvid (no.delete@this.hans.com) on January 24, 2017 1:55 am wrote:
> > Aaron Spink (aaronspink.delete@this.notearthlink.net) on January 23, 2017 7:02 pm wrote:
> > > dmcq (dmcq.delete@this.fano.co.uk) on January 22, 2017 1:03 pm wrote:
> > > > I'm not sure what "Problem with the phone/tablet SoCs is you are going to have to run at least
> > > > twice." means. Every ARM designed core has ECC support as an option as far as I'm aware, even
> > > > the A73 which is specifically for phones rather than mission critical or server applications.
> > > >
> > > That's great, what about the TB+ of main memory?
> > >
> >
> > Isn't it strange to ask of TB+ DRAM from smartphone SoC?
> > So far we have 8GB max here. Not that bad for a node.
> > Anyway CoreLink CMN-600 supports 8chn DDR4. So it should handle 1TB(?)
> >
> In the thread I'm replying to, we are talking about phone SoCs, the question about the TB+ of
> memory is related to main memory ECC for a super computer composed of phone/tablet socs.
>
> As far as X-Gene 3, that isn't a phone/tablet SoC. And it matters
> not what cores support, but what the processor/SoC supports.
>

Why would anyone build a TB+ single memory image supercomputer from phone SOCs, other than as
a strawman? There would be so many other things wrong with it anyway... memory addressing would
almost be the least of your problems.