itsmydamnation (no.delete@this.way.com) on January 26, 2017 3:55 pm wrote:
> none (none.delete@this.none.com) on January 26, 2017 5:39 am wrote:
> > Daniel B (fejenagy.delete@this.gmail.com) on January 26, 2017 3:37 am wrote:
> > > Michael S (already5chosen.delete@this.yahoo.com) on January 26, 2017 12:55 am wrote:
> > > > David Hess (davidwhess.delete@this.gmail.com) on January 25, 2017 9:47 pm wrote:
> > > > > none (none.delete@this.none.com) on January 24, 2017 10:48 pm wrote:
> > > > > >
> > > > > > Isn't Intel now using different masks, interconnects and other elements (L2 caches and AVX-512
> > > > > > for instance) for their server chips? Does this mean reusing most of their core
> > > > > > from laptops up to servers doesn't help them anymore? So does this mean the old story
> > > > > > that Intel is so strong because their server chips are basically the same as their PC chip
> > > > > > is now obsolete?
> > > > >
> > > > > Intel already *has* a large server market to support development of very expensive server oriented
> > > > > CPUs but the core design and validation is still shared with their desktop processors which are
> > > > > themselves identical to their low end Xeon processors except for market segmentation.
> > > > >
> > > >
> > > > Things used to be like that.
> > > > But, according to all reports, Skylake Xeons (not E3s) that are planned for release in Q2 or Q3
> > > > *do not* have the same core design as desktop processors. Not even the same instruction set.
> > > >
> > >
> > > My reading of what Intel engineers said about this matter (they were not cleared to share
> > > anything specific) was that Skylake server parts will indeed have different cores, but the
> > > differences are not going be fundamental to the x86 microarchitecture or L1/L2 cache for that
> > > matter. Are those reports saying otherwise? I haven't been paying attention. Do you have a
> > > link by chance? The engineers sort of confirmed it's macro blocks only at this stage.
> > >
> > > My speculation has always been that the biggest thing must be about AVX-512 vs. no AVX.
> > > I think that's now confirmed more or less. Another potential factor is that Purley will
> > > see extreme TDP SKUs (205W) which made me think if a different floorplan was needed for
> > > managing thermal stress. Potentially no and those are specifically liquid-cooled parts?
> >
> > That's my understanding too: L2 is increased to 1MB and AVX-512 is in. I have not heard
> > of anything beyond that as far as the core is concerned. They might have resized some
> > other structures (L2 TLB, or branch predictors), but that'd not be something I consider
> > fundamental.
> >
> > OTOH the impact on core validation is likely not trivial, but obviously not as heavy as
> > what would be needed for a really new core.
> >
> > > Anyway, this branching is still a major thing.
> >
> > Agreed.
>
> Aren't they also going to go to a more KNL style fabric for L3 instead of single/dual ring buses? I would
> expect the consumer to keep the ring bus as over recent generations they have actually decreased its performance
> and latency by moving its clocking domain from the cores to the uncore i assume save power.

I mentioned the change in the interconnect in my first message :-) But it's not a part
of the core itself which is what I was discussing later.