Mark Roulo (nothanks.delete@this.xxx.com) on January 27, 2017 9:02 am wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on January 27, 2017 6:46 am wrote:
> > The cache hierarchy is another example. The L2 caches in the latest z13 are simply massive.
> > The L2I and L2D are each 2MB and implemented in eDRAM for the arrays. The POWER8 has
> > a smaller L2, but has an L3 where the local portion is fairly large (8MB).
>
> Any yet ... Intel has eDRAM (Crystalwell), but doesn't ship
> server chips with large L4 caches made up of eDRAM.
>
> I'm assuming that they don't think there will be much of a performance advantage
> for server loads, but IBM does ship with much more on-package memory.
>
> Maybe because the eDRAM in Crystalwell is so wide?
>
> But we don't see MCDRAM (like on Knights Landing) as an option for Intel server chips, either ...
>
> Odd.

You can see eDRAM here:
http://www.anandtech.com/bench/product/1538?vs=1554

The effect on WinRar is clear