wumpus (lost.delete@this.in-a.cave.net) on January 29, 2017 6:57 am wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on January 29, 2017 2:43 am wrote:
> > Per Hesselgren (perhesselgren.delete@this.yahoo.se) on January 28, 2017 6:49 am wrote:
> > > Mark Roulo (nothanks.delete@this.xxx.com) on January 27, 2017 9:02 am wrote:
> > > > David Kanter (dkanter.delete@this.realworldtech.com) on January 27, 2017 6:46 am wrote:
>
> >
> > IMHO, it's quite clear, that inclusion of current form of eDRAM cache, i.e. off-die memory-side
> > cache, to general-purpose-oriented dual/quad-socket Xeon lines is *not* a good idea.
> >
> > For current form of Xeon-D is also does not sound as a good idea, but for
> > a different reason - [current form of] Xeon-D is very cost-sensitive.
> >
>
> Is there any advantage of off-die eDRAM over conventional DRAM? Obviously Intel fabs can manufacture off-chip
> eDRAM (and can't manufacture DRAM unless they bought a DRAM fab), but my understanding is that eDRAM gives
> up considerable density vs. DRAM. I'd also be fairly surprised if there is all that much a latency advantage
> (unless the DRAM manufacturers aren't interested in adjusting their masks for such small runs).

Latency and bandwidth.

http://www.anandtech.com/show/10435/assessing-ibms-power8-part-1/8

Keep in mind that
a) going off chip adds a lot of latency for the L4.
b) the L3 also uses eDRAM.