Latency vs. bandwidth

By: David Kanter (dkanter.delete@this.realworldtech.com), March 16, 2017 8:04 am
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on March 16, 2017 3:48 am wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on March 15, 2017 4:19 pm wrote:
> > Why do you suppose so?
> > It seems to me, it is technically possible to use the same electrical drivers/receivers
> > for both PCIe or HT3. In FPGAs they are doing it routinely for as long as they
> > started to support differential I/O at PCIe Gen2 or higher speed.
>
> Hasn't this been done for a while already? IIRC the SPARC T3 already had a bunch of SerDes
> that could be used for either the glueless interconnect or other purposes (PCIe? 10GbE?).

I'm not sure they were totally interchangeable in that way. The SPARC serdes were also very very fast (16-18gbps), which at least compensated a little for the intrinsically higher latency.

IBM and Intel both tend to prefer clock forwarded links for coherency since they have many snoop bound workloads.

David
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                            Thanks, your posts on this thread have been extremely informative (NT)Gabriele Svelto2017/03/17 01:08 PM
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