dmcq (dmcq.delete@this.fano.co.uk) on April 5, 2017 7:34 am wrote:
> Heikki Kultala (heikki.kultala.delete@this.tut.fi) on April 5, 2017 5:23 am wrote:
> > btw. How did the original MIPS handle data dependencies going from ALU(ex stage) to branch condition(decode
> > stage) ? Where they also specified to be unspecified during the next cycle?
> >
> > Or did they indeed to have interlocking for these?
> >
>
> I think they executed the branch in the decode stage - which led to it being rather complicated and the
> critical part of the pipeline with the decision for the branch being made near the end of the cycle.
>

I know, and this is exactly the point of my question - when a previous instruction generates a new loop index(in ex stage), and then the branch tries to read the new value of the loop index, it cannot do it when it's at decode stage at the same time as the previous instruction is at decode stage.