Seni (seniike.delete@this.hotmail.com) on April 9, 2017 4:06 am wrote:
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> The reason this did not apply for RISC is that separate instruction caches make it not
> really a Von-Neumann architecture. There are two memory buses in parallel, one for fetches
> and one for loads & stores, so single-cycle is possible even for load and store.

Brilliant.

This is exactly the explanation that I was searching for yesterday evening, in my mind. I was thinking of the Tensor Processing Unit paper that was published by the Google team - and the influence of thinking along the lines of what Seni described overhead in that.

Thanks for explaining the relationship of the cache to the RISC processor.