Additive clustering/replication advantages?

By: anon (spam.delete.delete@this.this.spam.com), April 27, 2017 10:54 am
anon2 (anon.delete@this.anon.com) on April 27, 2017 10:07 am wrote:
> anon (spam.delete.delete@this.this.spam.com) on April 27, 2017 8:05 am wrote:
> > anon2 (anon.delete@this.anon.com) on April 27, 2017 5:57 am wrote:
> > > anon (spam.delete.delete@this.this.spam.com) on April 27, 2017 4:08 am wrote:
> > > > anon2 (anon.delete@this.anon.com) on April 26, 2017 6:00 pm wrote:
> > > > > anon (spam.delete.delete@this.this.spam.com) on April 26, 2017 6:13 am wrote:
> > > > > > anon2 (anon.delete@this.anon.com) on April 26, 2017 5:17 am wrote:
> > > > > > > anon (spam.delete.delete@this.this.spam.com) on April 25, 2017 5:43 pm wrote:
> > > > > > > > Paul A. Clayton (paaronclayton.delete@this.gmail.com) on April 24, 2017 9:34 am wrote:
> > > > > > > > > anon (spam.delete.delete@this.this.spam.com) on April 24, 2017 1:00 am wrote:
> > [snip]
> > > > > > > > So if they get a group that does consist of 2 sub groups (it doesn't have to) then they can do
> > > > > > > > rename in parallel. Now that obviously doesn't work if the sub groups depend on each other.
> > > > > > >
> > > > > > > What do you mean by a sub-group? POWER8 dispatches 6+2 groups in ST mode and 2*(3+1)
> > > > > > > groups in SMT mode. SMT half groups do not depend on each other by definition.
> > > > > > >
> > > > > >
> > > > > > The GCT (IBM's name for their weird version of an ROB) handles groups instead of single
> > > > > > instructions. Each group (max 6+2 instr) consists of 1 or 2 sub groups (max 3+1 instr).
> > > > > > You can get 2 subgroup groups even in SMT mode. Since they have to dispatch into the same
> > > > > > slice they obviously need 2 cycles, but they only consume one entry in the GCT.
> > > > >
> > > > > Okay I never heard of this sub group idea, but for ST, it does not seems like a group or sub group is
> > > > > restricted according to any GPR input or output, so I don't see how it looks different to rename.
> > > > >
> > > >
> > > > One group dispatches in a single cycle in ST mode. Therefore not all instructions in it can
> > > > be dispatched into the same slice.
> > > > And that's when the fun starts. You could either wait
> > > > for the result forwarding and kill dependency chains with latency or restrict the grouping.
> > > > This ties into the ALU latency/issue ports problem, I can't rule out either option (forwarding
> > > > without grouping restrictions or 2 cycle ALU with restrictions) for certain.
> > >
> > > So I still don't know how that looks different for rename. You have a mix of GPR inputs
> > > and outputs being sent to each slice. How does that simplify rename for you?
> > >
> >
> > Would you send instructions that depend on each other to different
> > slices as much as possible because you like forwarding so much?
> > Obviously not.
> > If they don't you can rename in parallel.
>
> 1. "as much as possible"? Huh? Instructions go to slices
> not based on groups. Grouping does not solve anything.
>

They don't?
What does grouping do then?
It doesn't help decode, it's unrelated to dispatch, according to you it does nothing at all.

> 2. Renaming still has to be synchronized otherwise how do instructions
> in the next cycle know how registers are mapped?
>

Next cycle is the key here.

> > > You say like these "sub groups" are the basis of how dispatch chooses which UQ to dispatch to,
> > > but what I have seen says otherwise. For example POWER8 Core Microarchitecture whitepaper says
> > >
> > > "In ST mode, the two physical copies of the GPR and VSR have identical
> > > contents. Instructions from the thread can be dispatched to either one of the
> > > UniQueue halves (UQ0 or UQ1). Load balance across the two UniQueue
> > > halves is maintained by dispatching alternate instructions of a given type to
> > > alternating UniQueue halves."
> > >
> > > It chooses instructions only from one group per cycle, but there
> > > is no idea of sub groups that go to each issue queue.
> > >
> > > > If I recall correctly a group always ends on a branch even in ST mode, could be that it just
> > > > creates two sub groups then that can't dispatch in a single cycle. I'd have to look it up.
> > > >
> > > > > >
> > > > > > > In SMT mode, presumably registers operate independently and rename structures operate in halves, but
> > > > > > > nothing is bought for ST because it must still have the capacity to rename full dispatch width.
> > > > > > >
> > > > > >
> > > > > > In SMT mode the slices work independently. Each got its own PRFs, its own renamer
> > > > > > ("dispatcher"), its own scheduler ("issue queue") and its own execution units.
> > > > > > Some special function stuff, the branch unit and front end are shared.
> > > > >
> > > > > Right. Nothing to do with grouping though. A non-grouping microarchitecture could do exactly the
> > > > > same thing splitting the core in SMT and operating register files and renamers independently.
> > > > >
> > > >
> > > > Yes in SMT, but not in ST.
> > >
> > > How does POWER8 with groups allow it in ST?
> > >
> >
> > Grouping restrictions still apply in ST, that's the point.
>
> The point is illogical because grouping restrictions do not allow slices
> to work independently in ST mode. Grouping does not buy anything.
>

So why does grouping exist?

> >
> > > > Do you honestly believe that IBM can
> > > > just easily rename 8 instructions in a single cycle at 5 GHz?
> > >
> > > It can rename GPRs for 6 instructions per cycle.
> > >
> >
> > And Intel is still at 4 on 14nm if you want to count like that. Seems strange, doesn't it?
>
> No.
>

Ok then. Intel is just flailing about then or why don't they have 6 wide rename by now?

> >
> > > >
> > > > > >
> > > > > > In ST mode the PRFs have the same content so everything can execute on both slices. However because
> > > > > > of the way how rename works only one group can be renamed per cycle. That means if the group consists
> > > > > > of only one sub group, which it does most of the time, you only get 3+1 rename.
> > > > > >
> > > > > > Yes on paper it's "up to" 6+2, but that limit is rarely reached.
> > > > >
> > > > > That's besides the point though, if the renamer *can* map 6 GPR instructions in
> > > > > one cycle. That's my point. Grouping does not buy you anything of this sort.
> > > > >
> > > >
> > > > It's not one renamer.
> > >
> > > What keeps the two renamers in synch when they are being used for the same architected registers in ST mode?
> > >
> >
> > What keeps the PRFs in sync?
>
> Answer my question first. You are saying two renamers somehow work
> with grouping to reduce cost of rename. This doesn't follow.
>

Novel concept: You can forward results between slices if you don't already need it in the same cycle on the other slice.

> >
> > > >
> > > > > >
> > > > > > > When splitting the core in half, maybe the structures can operate more efficiently.
> > > > > > > But that is not related to grouping but to splitting by thread.
> > > > > > >
> > > > > >
> > > > > > Well if you want that many EUs the bypass network and all that would get extremely expensive.
> > > > > > It makes perfect to do it this way for SMT, when the EUs are actually useful.
> > > > > > For ST the overhead is huge compared to the actual miniscule speedup. Of course since
> > > > > > all that hardware is already there you might as well use it, but if you were to design
> > > > > > for ST performance this is probably the worst way of doing clustering.
> > > > >
> > > > > Nothing to do with grouping though.
> > > > >
> > > >
> > > > Clustering and dispatch are coupled, dispatch and grouping are coupled.
> > >
> > > And execution is decoupled, by out of order issue queues. Out of order part only acts on uops.
> > >
> >
> > How is it decoupled? One slice gets its uops from exactly one issue queue.
> > Any uops in the same sub group end up in the same slice.
>
> This assertion is wrong though. The IBM documentation says instructions are dispatched
> from groups based on some other policy, not a static group formation.
>

To quote:
"In ST each IOP is assigned to the opposite queue-half from the IOP before it."
So right after group formation you can already tell which IOPs will end up in the same queue and which won't.

> >
> > > >
> > > > > >
> > > > > > > Several people are asserting that grouping does something very helpful for rename
> > > > > > > on POWER8. What is it exactly? Where does this information come from?
> > > > > > >
> > > > > >
> > > > > > As mentioned above, it enables them to use two smaller renamers
> > > > > > instead of one large and insanely expensive one.
> > > > >
> > > > > I still don't see how this follows.
> > > > >
> > > >
> > > > See above.
> > > >
> > > > > >
> > > > > > >
> > > > > > > > And
> > > > > > > > then a subgroup still doesn't have to consist of 3+1 instructions, it could be less. You could
> > > > > > > > end up with 4 instructions total anyway. Hardly worth the effort, considering how many pipeline
> > > > > > > > stages grouping costs. On top of that they could still do rename like that with a single PRF.
> > > > > > > >
> > > > > > > > And then it goes on. 1 fixed point, 1 ld/st, 1 ld, 2 FP DP and 1 vector pipeline per slice look great
> > > > > > > > on paper until you realise that the issue width is 4 and they block each other
> > > > > > >
> > > > > > > Block each other? How? They cause cross-unit issue stalls or result hazards or something?
> > > > > > >
> > > > > >
> > > > > > I'm not sure how bad the port restrictions are, IBM mostly shows it as one pipe each for fixed,
> > > > > > FP/vector, ld and ld/st, but I don't know enough to confirm it. Issue width is definitely 4.
> > > > > > Either there are some shared ports so e.g. load and the second ALU block each other or each FU got
> > > > > > its own pipe with the 2 ALUs sharing one and only being able to execute one instruction every 2 cycles
> > > > > > each (not all that unlikely considering the frequency). Dependent instructions seem to take 2 cycles
> > > > > > so it's either caused by that or the front end weirdness, but I'm not willing to take a bet.
> > > > > >
> > > > > > Either way you end up with a lower average so the 3 wide dispatch is less
> > > > > > of a problem, but it looks less and less like an 8 wide design. That's why
> > > > > > I said actual 6 wide would be better for ST and not any more expensive.
> > > > >
> > > > > No it still looks like an 8 wide design because it can sustain 8 instructions per cycle
> > > > > through the pipeline. "Width" terminology is a very blunt instrument, but we can say
> > > > > for certain that it's not based around measuring achieved IPC on some codes.
> > > > >
> > > >
> > > > It can sustain 8 instruction only if you have exactly 1 branch and 1 cryptography instruction.
> > > > It can dispatch 2 branches to the branch unit, but it can only issue one per cycle. Same for CR.
> > >
> > > CR is actually condition register unit, not crypto. For some reason I thought those would
> > > group as branch instructions when I wrote that, but that's probably not right.
> > >
> >
> > Sorry, got confused for a second, it's been a while.
> > I also thought CR would be fused with BR, this way it's even worse.
> >
> > Crypto and decimal block another port on the issue queues I think.
> > Can't quite remember the details because they are shared between both slices.
> > "EDIT" Didn't want to pretend I knew this, had to look it up. DF/crypto block a VSU port.
> >
> > > > The two slices can issue 4, but it can only dispatch 3 to each.
> > > >
> > > > Don't use CR? Too bad.
> > > > Want more than 1 branch every 8 cycles? Too bad.
> > > > Your branches aren't space by 7 instructions? Too bad, the group ends on a branch.
> > > >
> > > > In SMT it's not nearly as bad but you're still limited to 7 without CR.
> > > > Due to branch spacing most code is inherently limited to about 6.
> > > >
> > > > Now the IPC is looking quite good, isn't it? The "theoretical maximum" is lower than you'd expect.
> > >
> > > Sure, but width is still not IPC.
> > >
> >
> > Of course.
> > My point was that while the IPC will obviously never be 8 that number is rather
> > theoretical and simply not possible without writing very weird code.
>
> That's what "width" has always been.
>
> > POWER8 is still nowhere near as effective at using its width in ST as in SMT mode. That's due to
> > the grouping but only because of the grouping it can be so wide and only for SMT it is so wide.
>
> This assertion is still not backed up anyhow. You handwavingly claim that grouping helps wider decode
> and wider rename, but as far as I can see, the reasons range from garbage to unfounded speculation.
>
> >
> > > >
> > > > > >
> > > > > > > > and even if they didn't
> > > > > > > > the issue queue can only take 3 new instructions per cycle anyway. So you have to rely on the existence
> > > > > > > > of enough 2 subgroup instructions (with enough instructions per subgroup) to get more than 3 instructions
> > > > > > > > (+1 branch) issued per cycle. Even then you have to deal with all the forwarding.
> > > > > > > > And now you know why POWER8 doesn't look all that hot in ST mode. Compare SMT2 with only a single thread
> > > > > > > > running on it to make it fair in terms of caches with ST mode. It doesn't do all that much.
> > > > > > >
> > > > > > > POWER8 is clearly long in the tooth against Intel. IIRC it
> > > > > > > was quite reasonable at single threaded perf against
> > > > > > > similar Xeons at the time of release, but now is behind and
> > > > > > > probably suffers a lot also from their much improved
> > > > > > > turbo. With its high frequencies, I don't think it was ever an IPC winner there, despite its width.
> > > > > > >
> > > > > >
> > > > > > Yes, e.g. in the Anandtech review it loses against Broadwell. In a fair comparision
> > > > > > against Ivy Bridge it would've been fairly close, but it's still dissapointing
> > > > > > when taking into account the ressources available per core.
> > > > > >
> > > > > > > But I don't know how much you can attribute to decode/dispatch restrictions or functional
> > > > > > > unit issue limitations, because it really made very big gains in SMT mode to the
> > > > > > > point where aggregate IPC should have been quite good at high clocks.
> > > > > > >
> > > > > >
> > > > > > In ST it just can't really use all its execution ressources due to
> > > > > > these restrictions. In SMT, which it was built for it's great.
> > > > >
> > > > > It was built for both.
> > > > >
> > > >
> > > > Yes and no. The slices were a perfectly reasonable way of getting the width they wanted/needed for SMT.
> > > > The weirdness on top of it was a reasonable way to make all the hardware
> > > > they already needed for SMT at least somewhat useful in ST.
> > > > But you wouldn't build it like that if the emphasis was
> > > > on ST. Slightly narrower/fewer, but shared ressources
> > > > would've been better for ST, but worse for SMT. If you get good enough ST performance this way why bother
> > > > redesigning everything and handicapping SMT instead of "simply" improving upon POWER7 like they did?
> > >
> > > Yes and yes. You also wouldn't build it like this if there was no
> > > interest in ST or no benefit for ST performance with this mode.
> > >
> >
> > You seem to be ignoring the point.
> > If there was no interest in ST but still in SMT then it would've been built exactly like this.
> > Only the parts to make both slices available to a single thread would've been left out.
> >
> > Whereas if there was no interest in SMT (or at least not SMT8)
> > then it sure as hell wouldn't have been built like this.
>
> Huh? That's exactly my point. It is obviously built for both.
>

I guess we're still misunderstanding each other.

So for just SMT you would've built it like that with some minor features left out.
For ST you would've built something completely different

What was the focus on?

> >
> > > >
> > > > > >
> > > > > > > I think it's more likely that there is just very diminishing returns of such width for ST, combined
> > > > > > > with weaknesses like bubbles in dependent ALU ops (IIRC this was improved but still had a bubble
> > > > > > > somewhere, maybe had a cycle forwarding between halves), longer mispredict, longer and I think
> > > > > > > more restrictive store forwarding, and all the other things that Intel does so well.
> > > > > > >
> > > > > >
> > > > > > Yeah, it's either weird front end stuff and/or forwarding where that extra cycle comes from or 2 cycle ALUs.
> > > > > >
> > > > > > > >
> > > > > > > > At this point one might think instruction grouping isn't really worth
> > > > > > > > the effort and a slightly wider single slice might be better.
> > > > > > > > Guess what they did on POWER9? Instruction grouping gone and all the pipeline stages for it.
> > > > > > >
> > > > > > > Well the POWER9 pipeline looks like a complete redesign. According to hotchips, it's 3 cycles
> > > > > > > shorter pipeline before rename. POWER8 explicitly takes 2 stages for group formation. But that
> > > > > > > seems hard to quantify exactly. Presumably grouping is done to make subsequent things easier.
> > > > > > >
> > > > > > > > They
> > > > > > > > sacrificed 8 wide decode for that,
> > > > > > >
> > > > > > > Seems unlikely that removal of groups makes wide decode more difficult.
> > > > > > >
> > > > > >
> > > > > > Well grouping does some decode work, you can't drop those cycles without either losing
> > > > > > that or doing it in the other decode stages,
> > > > > > which IBM seems to have decided against.
> > > > >
> > > > > Still doesn't follow. If that was indeed the case, then they did not "sacrifice" 8 way rename
> > > > > for dropping of groups, they sacrificed it for making a shorter decode pipeline.
> > > > >
> > > >
> > > > Should I have been more clear?
> > > > Dropping grouping is not a goal in itself.
> > > > They wanted a short pipeline so they dropped grouping. No grouping means more difficult decode.
> > >
> > > Completely disagree. You assert this and then you handwave about how grouping
> > > "does some decode work" to justify it, which is just circular logic.
> > >
> > > > So either you add a pipeline stage, which contradicts your goal, or you accept narrower decode.
> > >
> > > You add a pipeline stage to make up for this alleged work done by grouping which you removed
> > > at least 2 pipeline stages from, and that somehow means that grouping made decode easier?
> > >
> >
> > Grouping is based in instruction types.
> > So grouping is done before decode and somehow it magically knows the instruction type already?
>
> What are you talking about? Please don't try to make statements with rhetorical questions.
>
> Grouping is done before decode stages, on official pipeline description, yes. There is
> some predecode or early decode that helps branch prediction and group formation. So of
> course there is some amount of decode before that. It's very trivial to find fixed instruction
> types of powerpc instructions. Real decoding is turning those into uops.
>
> > Of course decoding gets easier when you know which instruction
> > type to expect, branches are in fixed positions and so on.
>
> That's nothing enabled by groups. Quite possibly POWER9 does
> predecoding and has some metadata for branch prediction.
>

They have metadata for branches but not much else.

> > Seriously, take the last slot as an example. What do think is simpler, a decoder that must be
> > able to decode any instruction or a decoder that has to decode either a branch or nothing?
>
> That's not an example, it's handwaving. The same work has to be done in the pipeline.
>
> >
> > Yes, most of the work done in the grouping stages is for grouping. It still helped decode a bit.
>
> Still baseless assertion.
>
> > So the choice is either longer logical effort effort meaning longer cycle time
> > or more stages for decode, although less than with grouping, or narrower decode.
> > Why bother with the first two when 8 wide decode isn't needed anymore?
>
> Your question is based on baseless assertions.
>
> >
> > > > Since they went with actual 6 wide rename instead of "8 but it's
> > > > mostly 6" the 8 wide decode became a lot less useful anyway.
> > >
> > > No, it's 6 for GPRs, and one for condition registers. Well two can play at such assertions,
> > > so I'll say no it's due to improved efficiency from less grouping and cracking. Possibly
> > > also due to going generally a bit narrower and reducing SMT emphasis per core.
> > >
> >
> > Do you mean POWER8 or 9?
>
> 8.
>
> > 9 should be 6 including max 2 branches, 8 is 6
> > + 2 branch or condition, so I'm not seeing 1 cr rename there either.
> > Either way, what good would 8 wide decode do when you can only rename 6 anyway?
>
> Err, are we on the same planet? It is 8 wide decode to decode 6 non-branch and 2 branch
> instructions. Branch instructions use a single input of renamed CR of course, but given
> it goes to separate issue queue than the 2 unified queues with their duplicated registers,
> and has the explicit condition register moves and high latencies, almost certainly it is
> a different register file and renamer for it so not involved with 6-wide GPR rename.
>

The last sentence was referring to POWER9. I should've switched the order.

> > Makes sense that they dropped it.
>
> Really? Last you said they "sacrificed" it as a necessary part of getting rid of grouping.
>

Yes? And it makes sense. Because they couldn't afford 8 wide rename and without it 8 wide decode would be useless.

Explain to me what you think grouping does.
Why do they waste 2 cycles on it when it improves nothing apparently?
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RISC *was* science, not religionMegol2017/04/11 11:23 AM
RISC *was* science, not religionGabriele Svelto2017/04/11 12:49 PM
The Mill is not dataflowPaul A. Clayton2017/04/12 03:43 AM
The Mill is not dataflowAdrian2017/04/12 10:21 AM
Name rather than address for Mill pick-up loads?Paul A. Clayton2017/04/12 06:35 PM
Name rather than address for Mill pick-up loads?Adrian2017/04/12 10:51 PM
Fractional bits for instruction encodingook2017/04/13 12:56 AM
Fractional bits have been used for RegID encoding (NT)Paul A. Clayton2017/04/13 03:04 AM
Fractional bits for instruction encodingMegol2017/04/13 04:21 AM
fractional bitsRichardC2017/04/13 05:20 AM
fractional bitsMegol2017/04/15 05:22 AM
fractional bitsRichardC2017/04/15 09:58 AM
fractional bitsAdrian2017/04/16 03:08 AM
fractional bitsdmcq2017/04/16 04:04 AM
fractional bitsMichael_S2017/04/16 04:27 AM
The Mill spills load buffers on function callsPaul A. Clayton2017/04/16 11:44 AM
The Mill spills load buffers on function callsRichardC2017/04/16 01:36 PM
A specialized cache for spillsPaul A. Clayton2017/04/16 03:52 PM
A specialized cache for spillsRichardC2017/04/17 12:16 AM
The cycle-predictable domainRichardC2017/04/17 07:29 AM
The cycle-predictable domainMichael S2017/04/17 01:35 PM
The cycle-predictable domainRichardC2017/04/17 02:01 PM
The cycle-predictable domainMichael S2017/04/17 02:37 PM
The cycle-predictable domainRichardC2017/04/17 04:25 PM
The cycle-predictable domainRichardC2017/04/20 08:10 AM
The cycle-predictable domainMichael S2017/04/21 04:15 AM
sgemm detailsRichardC2017/04/21 05:09 AM
sgemm detailsRichardC2017/04/21 08:45 AM
sgemm detailsRichardC2017/04/21 10:27 AM
sgemm detailsMichael S2017/04/22 09:43 AM
sgemm detailsRichardC2017/04/23 05:18 AM
sgemm detailsanon2017/04/23 05:51 AM
sgemm detailsMichael S2017/04/23 05:59 AM
sgemm detailsTravis2017/04/25 07:26 PM
sgemm detailsMichael S2017/04/26 12:10 AM
sgemm detailsTravis2017/04/26 11:33 AM
sgemm detailsMichael S2017/04/26 12:37 PM
sgemm detailsanon2017/04/27 08:17 AM
sgemm detailsanon2017/04/26 10:35 AM
sgemm detailsTravis2017/04/26 12:00 PM
sgemm detailsTravis2017/04/26 12:50 PM
sgemm detailsTravis2017/04/26 12:55 PM
sgemm detailsTravis2017/04/26 12:58 PM
sgemm detailsanon2017/04/26 01:20 PM
sgemm detailsMichael S2017/04/23 05:55 AM
Mill "registers"Michael S2017/04/22 10:45 AM
The cycle-predictable domainJacob Marley2017/04/17 08:28 PM
The cycle-predictable domainJacob Marley2017/04/17 08:28 PM
The cycle-predictable domainMaynard Handley2017/04/17 09:00 PM
OoO window and cachesRichardC2017/04/18 05:53 AM
Mill made more sense in 2003RichardC2017/04/18 01:48 PM
Mill made more sense in 2003Megol2017/04/18 02:24 PM
Mill made more sense in 2003RichardC2017/04/18 03:46 PM
Mill made more sense in 2003Megol2017/04/19 09:02 AM
Mill made more sense in 2003RichardC2017/04/19 12:22 PM
Mill made more sense in 2003anon2017/04/20 05:35 AM
Mill made more sense in 2003RichardC2017/04/20 08:39 AM
Mill made more sense in 2003anon2017/04/20 11:15 AM
Mill made more sense in 2003RichardC2017/04/20 12:10 PM
Mill made more sense in 2003anon2017/04/20 02:27 PM
Mill made more sense in 2003RichardC2017/04/20 06:33 PM
Mill made more sense in 2003anon2017/04/21 02:35 AM
Mill made more sense in 2003RichardC2017/04/21 04:25 AM
DenverRichardC2017/04/21 04:54 AM
Denverdmcq2017/04/22 03:57 AM
DenverMichael S2017/04/22 10:58 AM
Denverdmcq2017/04/22 11:57 AM
DenverRichardC2017/04/22 01:41 PM
Denverdmcq2017/04/22 02:35 PM
Denverdmcq2017/04/22 02:41 PM
loopsRichardC2017/04/23 05:03 AM
loopsanon2017/04/23 05:35 AM
loopsRichardC2017/04/25 05:41 PM
loopsanon2017/04/26 04:08 AM
loopsBrett2017/04/26 12:27 PM
loopsanon2017/04/26 01:16 PM
loopsBrett2017/04/27 12:11 AM
DenverMichael S2017/04/22 02:41 PM
Phasing *is* similar to classic skewed pipelinesPaul A. Clayton2017/04/24 10:52 AM
Phasing *is* similar to classic skewed pipelinesRichardC2017/04/25 05:50 PM
Phasing *is* similar to classic skewed pipelinesMegol2017/04/26 03:58 AM
Phasing *is* similar to classic skewed pipelinesanon2017/04/26 04:18 AM
Phasing *is* similar to classic skewed pipelinesRichardC2017/04/26 12:22 PM
Phasing *is* similar to classic skewed pipelinesBrett2017/04/26 12:38 PM
Phasing *is* similar to classic skewed pipelinesMichael S2017/04/26 01:13 PM
Phasing *is* similar to classic skewed pipelinesRichardC2017/04/26 03:19 PM
Mill made more sense in 2003anon2017/04/21 06:55 AM
Mill made more sense in 2003RichardC2017/04/21 07:56 AM
Mill made more sense in 2003anon2017/04/21 10:46 AM
Mill made more sense in 2003RichardC2017/04/21 01:13 PM
Mill made more sense in 2003anon2017/04/21 01:21 PM
Mill made more sense in 2003none2017/04/21 08:03 AM
Mill made more sense in 2003NoSpammer2017/04/21 11:40 AM
Mill made more sense in 2003anon2017/04/21 12:19 PM
Mill made more sense in 2003Brett2017/05/06 02:16 PM
Mill made more sense in 2003anon2017/05/06 03:41 PM
Mill made more sense in 2003wumpus2017/05/06 06:05 PM
Mill made more sense in 2003Brett2017/05/07 12:56 PM
Mill made more sense in 2003anon2017/05/07 04:47 PM
Mill made more sense in 2003Brett2017/05/07 07:57 PM
Mill made more sense in 2003anon2017/05/08 12:39 AM
Mill made more sense in 2003Brett2017/05/08 01:38 AM
Mill made more sense in 2003anon2017/05/08 02:15 AM
Mill made more sense in 2003wumpus2017/05/08 06:53 AM
Mill made more sense in 2003Brett2017/05/08 10:34 PM
Mill made more sense in 2003anon2017/05/09 05:53 AM
Mill made more sense in 2003Brett2017/05/10 08:34 PM
Mill made more sense in 2003anon2017/05/11 09:28 AM
Mill made more sense in 2003Brett2017/05/11 09:31 AM
Mill made more sense in 2003anon2017/05/11 01:46 PM
Mill made more sense in 2003Brett2017/05/11 09:12 PM
Mill made more sense in 2003anon2017/05/12 09:06 AM
Mill made more sense in 2003Brett2017/05/14 06:42 PM
Mill made more sense in 2003anon2017/05/15 07:51 AM
Mill made more sense in 2003Brett2017/05/15 08:56 AM
Mill made more sense in 2003anon2017/05/15 11:50 AM
Mill static schedulingPaul A. Clayton2017/05/15 11:00 AM
integer multiplication latence, welcome to this millenniumHeikki Kultala2017/05/15 11:24 AM
integer multiplication latence, welcome to this millenniumRichardC2017/05/15 01:38 PM
stalling after variable latency instruction in millHeikki Kultala2017/05/15 08:56 PM
stalling after variable latency instruction in millanon2017/05/16 12:31 AM
stalling after variable latency instruction in millMichael S2017/05/16 12:34 AM
stalling after variable latency instruction in millRichardC2017/05/16 08:19 AM
integer multiplication latence, welcome to this millenniumBrett2017/05/15 09:23 PM
integer multiplication latence, welcome to this millenniumHeikki Kultala2017/05/15 11:10 PM
integer multiplication latence, welcome to this millenniumBrett2017/05/17 09:56 AM
integer multiplication latence, welcome to this millenniumanon2017/05/16 12:44 AM
integer multiplication latence, welcome to this millenniumBrett2017/05/16 10:37 PM
integer multiplication latence, welcome to this millenniumBrett2017/05/20 04:23 PM
fast multiplier sizeHeikki Kultala2017/05/16 03:43 AM
Mill made more sense in 2003Jacob Marley2017/05/06 07:16 PM
the dataflow graphRichardC2017/05/08 04:59 PM
the dataflow graphJacob Marley2017/05/08 08:49 PM
the dataflow graphRichardC2017/05/09 03:28 AM
the dataflow graphJacob Marley2017/05/14 02:12 AM
dataflow languages?j2017/05/09 01:58 AM
dataflow languages?anon.12017/05/10 07:09 AM
dataflow languages?j2017/05/12 04:00 AM
dataflow languages?RichardC2017/05/12 02:02 PM
dataflow languages? (R in particular)wumpus2017/05/14 08:50 AM
R/Python dynamic workload is Fortran-like ?RichardC2017/05/14 04:59 PM
dataflow languages? (R in particular)slacker2017/05/14 08:52 PM
Mill made more sense in 2003Megol2017/04/22 03:42 AM
Mill made more sense in 2003RichardC2017/04/22 10:07 AM
Actually, Mill scratchpad is more like 1 cycleHenry S2017/04/21 01:27 PM
Mill made more sense in 2003Jacob Marley2017/04/20 09:14 PM
Mill made more sense in 2003Jacob Marley2017/04/20 09:14 PM
Mill made more sense in 2003Jacob Marley2017/04/20 09:15 PM
OoOE processor and virtual function callsHeikki kultala2017/04/20 09:59 PM
OoOE processor and virtual function callsJacob Marley2017/04/21 12:12 AM
OoOE processor and virtual function callsMichael_S2017/04/21 02:04 AM
OoOE processor and virtual function callsRichardC2017/04/21 05:26 AM
Mill made more sense in 2003Michael_S2017/04/21 02:37 AM
Mill made more sense in 2003Gabriele Svelto2017/04/22 02:17 PM
Glew quote about amount of OoOPaul A. Clayton2017/04/24 09:55 AM
Glew thoughts on OoO vs tradittional Runahead vs improved Runaheadjuanrga2017/04/25 09:58 AM
Glew thoughts on OoO vs tradittional Runahead vs improved RunaheadPaul A. Clayton2017/04/26 05:32 PM
Glew thoughts on OoO vs tradittional Runahead vs improved Runaheadjuanrga2017/04/28 04:06 AM
Glew quote about amount of OoOanon2017/04/25 02:06 PM
Glew quote about amount of OoOLinus Torvalds2017/04/25 04:11 PM
How ARM Cortex-A53 fits in the picture? (NT)Michael S2017/04/25 11:40 PM
I think you put your finger on itHenry S2017/04/26 01:16 AM
I think you put your finger on itJacob Marley2017/04/26 11:02 PM
I think you put your finger on itHenry S2017/04/27 06:29 PM
I think you put your finger on itJacob Marley2017/04/29 05:17 PM
A Mill-specific weakness?Paul A. Clayton2017/04/29 05:41 PM
Glew quote about amount of OoOEtienne2017/04/26 01:53 AM
Glew quote about amount of OoOMichael S2017/04/26 02:29 AM
Glew quote about amount of OoOdmcq2017/04/26 03:52 AM
Glew quote about amount of OoOanon2017/04/26 05:20 AM
Glew quote about amount of OoOnobody in particular2017/04/26 05:45 AM
Glew quote about amount of OoOanon2017/04/26 06:07 AM
Glew quote about amount of OoOwumpus2017/04/26 06:32 AM
Glew quote about amount of OoOanon2017/04/26 07:21 AM
Glew quote about amount of OoOnobody in particular2017/04/26 04:53 PM
Glew quote about amount of OoOLinus Torvalds2017/04/26 10:44 AM
Glew quote about amount of OoOanon2017/04/26 10:56 AM
Glew quote about amount of OoOLinus Torvalds2017/04/26 01:26 PM
Glew quote about amount of OoOanon2017/04/27 01:30 AM
Glew quote about amount of OoOLinus Torvalds2017/04/27 10:04 AM
Glew quote about amount of OoOanon2017/04/27 10:26 AM
Glew quote about amount of OoOLinus Torvalds2017/04/27 11:17 AM
Glew quote about amount of OoOanon2017/04/27 11:28 AM
Glew quote about amount of OoOLinus Torvalds2017/04/27 12:07 PM
Flying Scotsman Ireland2017/04/27 12:56 PM
Glew quote about amount of OoOanon2017/04/27 01:39 PM
Glew quote about amount of OoOIreland2017/04/27 02:18 PM
Glew quote about amount of OoOLinus Torvalds2017/04/27 02:37 PM
Glew quote about amount of OoOanon2017/04/27 03:03 PM
Glew quote about amount of OoOLinus Torvalds2017/04/27 03:54 PM
Glew quote about amount of OoOIreland2017/04/27 04:36 PM
Glew quote about amount of OoOrwessel2017/04/27 05:01 PM
Glew quote about amount of OoOdmcq2017/04/28 03:19 AM
Glew quote about amount of OoOIreland2017/04/28 06:37 AM
Glew quote about amount of OoOIreland2017/04/28 07:26 AM
Glew quote about amount of OoOBrett2017/04/28 09:17 AM
Glew quote about amount of OoOMaynard Handley2017/04/28 10:58 AM
Glew quote about amount of OoOIreland2017/04/28 12:27 PM
Glew quote about amount of OoOwumpus2017/04/28 06:39 PM
Glew quote about amount of OoOJukka Larja2017/04/28 08:03 PM
Glew quote about amount of OoOrwessel2017/04/28 09:10 PM
Glew quote about amount of OoOJukka Larja2017/04/29 03:30 AM
Glew quote about amount of OoOgallier22017/05/08 12:49 AM
Glew quote about amount of OoOMaynard Handley2017/04/28 09:14 PM
Glew quote about amount of OoOJukka Larja2017/04/29 03:27 AM
Glew quote about amount of OoOwumpus2017/04/29 09:03 AM
Glew quote about amount of OoOIreland2017/04/29 05:57 PM
Glew quote about amount of OoOMaynard Handley2017/04/29 08:28 PM
Glew quote about amount of OoOIreland2017/04/30 07:46 AM
Methods for exchange of data Ireland2017/04/30 07:59 AM
Glew quote about amount of OoOwumpus2017/04/27 07:40 PM
Glew quote about amount of OoOGabriele Svelto2017/04/28 12:58 AM
Glew quote about amount of OoOwumpus2017/04/28 06:38 AM
Glew quote about amount of OoOLinus Torvalds2017/04/28 09:12 AM
Glew quote about amount of OoOdmcq2017/04/28 10:31 AM
Glew quote about amount of OoOLinus B Torvalds2017/04/28 04:16 PM
Glew quote about amount of OoOdmcq2017/04/29 07:30 AM
Glew quote about amount of OoOwumpus2017/04/28 06:29 PM
Glew quote about amount of OoOSeni2017/04/29 04:36 AM
Critical misunderstandings@2017/04/29 08:42 AM
Critical misunderstandingsMegol2017/04/29 01:18 PM
Critical misunderstandingsExophase2017/04/29 08:22 PM
Critical misunderstandingsMaynard Handley2017/04/29 09:01 PM
Critical misunderstandings@2017/04/30 05:03 AM
Glew quote about amount of OoOGabriele Svelto2017/04/28 12:46 AM
Glew quote about amount of OoOanon2017/04/28 01:40 AM
Glew quote about amount of OoOanon22017/04/27 02:39 PM
Glew quote about amount of OoOanon2017/04/27 03:10 PM
Glew quote about amount of OoOanon22017/04/27 03:57 PM
Glew quote about amount of OoOanon22017/04/27 04:00 PM
Glew quote about amount of OoOanon2017/04/28 01:06 AM
Glew quote about amount of OoOanon22017/04/28 04:42 AM
Glew quote about amount of OoOanon2017/04/28 09:15 AM
Glew quote about amount of OoOanon22017/04/28 05:05 PM
Glew quote about amount of OoOWilco2017/04/27 03:56 PM
Glew quote about amount of OoOanon22017/04/27 04:57 PM
Glew quote about amount of OoOEtienne2017/04/28 12:56 AM
Glew quote about amount of OoOWilco2017/04/28 02:24 AM
Glew quote about amount of OoOanon2017/04/28 02:40 AM
Glew quote about amount of OoOEtienne2017/04/28 04:29 AM
Glew quote about amount of OoOLinus B Torvalds2017/04/29 01:12 PM
Glew quote about amount of OoOanon22017/04/28 04:57 AM
Glew quote about amount of OoOWilco2017/04/28 01:25 PM
Moar cores and A53Heikki kultala2017/04/29 10:03 AM
Bad comparison points of A53 and A72.Heikki kultala2017/04/29 10:01 AM
Bad comparison points of A53 and A72.juanrga2017/04/30 04:02 AM
Bad comparison points of A53 and A72.anon22017/04/30 04:31 AM
Did AAPL ever confirmed that Zephyr is OoO ? (NT)Michael S2017/04/30 06:26 AM
Did AAPL ever confirmed that Zephyr is OoO ?Maynard Handley2017/04/30 09:08 AM
Glew quote about amount of OoOHeikki kultala2017/04/29 10:17 AM
Glew quote about amount of OoOMaynard Handley2017/04/29 11:51 AM
Glew quote about amount of OoOWilco2017/04/30 11:28 AM
Glew quote about amount of OoODavid Hess2017/04/30 12:14 PM
Glew quote about amount of OoOWilco2017/05/01 03:42 AM
anon22017/05/01 04:59 AM
Posted without topic (was Glew quote about amount of OoO)anon22017/05/01 05:01 AM
Glew quote about amount of OoODavid Hess2017/05/01 08:36 AM
Glew quote about amount of OoOHeikki kultala2017/05/01 07:27 PM
Glew quote about amount of OoOWilco2017/05/02 12:29 AM
Glew quote about amount of OoOanon22017/05/02 12:57 AM
Glew quote about amount of OoOMichael_S2017/05/02 05:24 AM
Glew quote about amount of OoOLinus B Torvalds2017/05/02 10:07 AM
Glew quote about amount of OoOMichael S2017/05/02 10:32 AM
Glew quote about amount of OoOLinus B Torvalds2017/05/02 10:53 AM
Glew quote about amount of OoOMichael S2017/05/02 11:05 AM
Glew quote about amount of OoOdmcq2017/05/04 07:04 AM
Glew quote about amount of OoOIreland2017/05/04 10:00 AM
Glew quote about amount of OoOAdrian2017/05/04 09:50 AM
Glew quote about amount of OoOIreland2017/05/04 10:04 AM
You're not alone!iz2017/05/04 01:05 PM
You're not alone!GTR2017/05/09 02:21 PM
Glew quote about amount of OoOIreland2017/05/02 11:52 AM
Glew quote about amount of OoODoug S2017/05/02 02:13 PM
Glew quote about amount of OoOMaynard Handley2017/05/02 04:08 PM
Glew quote about amount of OoOslacker2017/05/02 10:06 PM
Glew quote about amount of OoOBrett2017/05/02 11:14 PM
Glew quote about amount of OoOanonymouse2017/05/05 05:02 AM
Glew quote about amount of OoOMaynard Handley2017/05/02 11:24 PM
Rigorous dataslacker2017/05/03 01:03 AM
Glew quote about amount of OoOSymmetry2017/05/03 04:38 AM
Glew quote about amount of OoOslacker2017/05/02 05:00 PM
Glew quote about amount of OoOLinus B Torvalds2017/05/02 06:08 PM
Glew quote about amount of OoOslacker2017/05/02 10:20 PM
Glew quote about amount of OoOSymmetry2017/05/03 04:53 AM
Glew quote about amount of OoOGabriele Svelto2017/05/04 11:42 PM
Glew quote about amount of OoOjuanrga2017/05/03 01:32 AM
Latency versus Efficiency Ireland2017/05/03 02:44 AM
Latency versus Efficiency Ireland2017/05/03 02:49 AM
Latency versus Efficiency juanrga2017/05/06 02:57 AM
Latency versus Efficiency Linus B Torvalds2017/05/06 09:55 AM
Latency versus Efficiency Ireland2017/05/06 10:37 AM
Efficiency != Throughput (NT)juanrga2017/05/07 03:03 AM
Efficiency != ThroughputLinus B Torvalds2017/05/07 08:18 AM
Efficiency != ThroughputAdrian2017/05/07 10:10 AM
Efficiency != Throughputanon2017/05/07 04:04 PM
Efficiency != ThroughputJacob Marley2017/05/07 05:48 PM
Efficiency != ThroughputAnne O. Nymous2017/05/08 02:25 AM
Crocodiliaslacker2017/05/08 02:39 AM
Crocodiliaanon2017/05/08 02:59 AM
Efficiency != ThroughputLinus B Torvalds2017/05/08 10:17 AM
Efficiency != ThroughputIreland2017/05/08 12:44 PM
Efficiency != ThroughputDomaldel2017/05/08 10:30 PM
Efficiency != ThroughputIreland2017/05/07 11:28 AM
Efficiency != ThroughputDomaldel2017/05/08 10:35 PM
Efficiency != ThroughputDomaldel2017/05/08 10:19 PM
Efficiency != ThroughputLinus B Torvalds2017/05/09 08:47 AM
Efficiency != ThroughputIreland2017/05/09 11:22 AM
analogyMichael S2017/05/10 04:05 AM
analogyIreland2017/05/10 05:25 AM
It is not "high-performance vs low-performance"juanrga2017/05/09 02:37 AM
It is not "high-performance vs low-performance"anon2017/05/09 04:51 PM
It is not "high-performance vs low-performance"juanrga2017/05/12 05:57 PM
It is not "high-performance vs low-performance"Anon2017/05/10 06:25 AM
It IS "high-performance vs low-performance"Heikki Kultala2017/05/10 08:20 PM
Latency versus Efficiency Symmetry2017/05/08 05:40 AM
Latency versus Efficiency Gabriele Svelto2017/05/08 07:56 AM
Latency versus Efficiency juanrga2017/05/09 01:29 AM
Latency versus Efficiency GTR2017/05/09 02:17 PM
Latency versus Efficiency anon2017/05/09 02:46 PM
Latency versus Efficiency Maynard Handley2017/05/09 04:15 PM
Glew quote about amount of OoOanonymouse2017/05/05 03:17 PM
Glew quote about amount of OoOjuanrga2017/05/06 02:57 AM
Glew quote about amount of OoOEtienne2017/05/08 12:57 AM
Glew quote about amount of OoOGabriele Svelto2017/05/08 05:21 AM
Glew quote about amount of OoOGTR2017/05/09 02:09 PM
your 3x is total bullshitHeikki kultala2017/05/02 12:30 PM
your 3x is total bullshitWilco2017/05/02 01:58 PM
your 3x is total bullshitMichael S2017/05/02 02:58 PM
your 3x is total bullshitWilco2017/05/03 02:13 AM
your 3x is total bullshitMichael S2017/05/03 03:43 AM
your 3x is total bullshitMichael S2017/05/03 05:15 AM
your 3x is total bullshitWilco2017/05/03 01:31 PM
your 3x is total bullshitMichael S2017/05/04 06:56 AM
your 3x is total bullshitLinus B Torvalds2017/05/04 09:46 AM
your 3x is total bullshitMaynard Handley2017/05/02 04:19 PM
your 3x is total bullshitHeikki kultala2017/05/02 09:57 PM
your 3x is total bullshitGabriele Svelto2017/05/05 05:32 AM
your 3x is total bullshitjuanrga2017/05/06 02:45 AM
your 3x is total bullshitGabriele Svelto2017/05/08 05:12 AM
Or, alternatively, your 65% is bullshit.Heikki kultala2017/05/02 12:37 PM
Or, alternatively, your 65% is bullshit.Wilco2017/05/02 02:39 PM
Going from 2-wide in-order to 2-wide OoOE benchmarks..Heikki kultala2017/05/02 12:42 PM
Going from 2-wide in-order to 2-wide OoOE benchmarks..Megol2017/05/13 12:26 PM
Going from 2-wide in-order to 2-wide OoOE benchmarks..Michael S2017/05/13 01:14 PM
Glew quote about amount of OoOMichael S2017/04/28 04:12 AM
Glew quote about amount of OoOGabriele Svelto2017/04/28 04:25 AM
Glew quote about amount of OoOLinus Torvalds2017/04/28 08:47 AM
Glew quote about amount of OoOEtienne2017/05/02 07:36 AM
Glew quote about amount of OoOMaynard Handley2017/04/28 01:02 AM
Glew quote about amount of OoOwumpus2017/04/28 06:54 PM
3-wide in-orderMichael S2017/05/02 02:51 AM
3-wide in-orderwumpus2017/05/03 06:24 AM
Merced is actually 6-way core (NT)Michael S2017/05/03 10:35 AM
only on a really good daysomeone2017/05/04 07:11 AM
It's the memory! stupid.gallier22017/04/28 07:56 AM
Merced is actually 6-way core (NT)Michael S2017/05/03 06:47 AM
Glew quote about amount of OoOMr. Camel2017/04/28 12:55 PM
Glew quote about amount of OoOMaynard Handley2017/04/28 02:00 PM
Glew quote about amount of OoOLinus B Torvalds2017/04/29 12:58 PM
Glew quote about amount of OoOIreland2017/04/29 01:38 PM
P4 part is complete bullshit (NT)Michael S2017/04/29 02:04 PM
Glew quote about amount of OoOMr. Camel2017/04/29 02:22 PM
Glew quote about amount of OoOLinus B Torvalds2017/04/29 02:46 PM
Glew quote about amount of OoOIreland2017/04/29 03:06 PM
Glew quote about amount of OoOAnil Maliyekkel2017/04/29 04:04 PM
Glew quote about amount of OoOGabriele Svelto2017/04/30 05:59 AM
License-optimized core designsGTR2017/05/09 01:18 PM
License-optimized core designsSimon Farnsworth2017/05/10 01:33 AM
Glew quote about amount of OoOanon.12017/04/26 10:15 PM
Glew quote about amount of OoOanon2017/04/27 12:14 AM
Jetson TX2 Linux Benchmarks on phoronixMichael S2017/04/27 01:02 AM
Jetson TX2 Linux Benchmarks on phoronixMichael S2017/04/27 01:04 AM
Jetson TX2 Linux Benchmarks on phoronixanon2017/04/27 01:49 AM
Jetson TX2 Linux Benchmarks on phoronixMichael S2017/04/27 03:41 AM
Jetson TX2 Linux Benchmarks on phoronixanon2017/04/27 04:15 AM
Jetson TX2 Linux Benchmarks on phoronixMichael S2017/04/27 05:10 AM
Jetson TX2 Linux Benchmarks on phoronixanon2017/04/27 06:02 AM
Glew quote about amount of OoOwumpus2017/04/27 06:48 AM
Glew quote about amount of OoOanon2017/04/27 08:49 AM
Glew quote about amount of OoOanon.12017/04/27 09:47 PM
Glew quote about amount of OoOwumpus2017/04/28 06:49 AM
Glew quote about amount of OoOHeikki kultala2017/04/30 12:13 AM
Glew quote about amount of OoOanon2017/04/30 02:27 AM
Glew quote about amount of OoOanon.12017/04/27 07:16 AM
Glew quote about amount of OoOanon2017/04/27 08:44 AM
Glew quote about amount of OoOSymmetry2017/04/27 09:48 AM
Glew quote about amount of OoOIreland2017/04/26 03:55 PM
Glew quote about amount of OoOIreland2017/04/26 04:16 PM
Glew quote about amount of OoOIreland2017/04/26 04:41 PM
Glew quote about amount of OoOjuanrga2017/04/28 04:22 AM
Glew quote about amount of OoOHeikki kultala2017/04/29 08:14 AM
Glew quote about amount of OoOjuanrga2017/04/30 03:44 AM
Glew quote about amount of OoODavid Hess2017/04/30 12:28 PM
Glew quote about amount of OoOIreland2017/04/30 03:15 PM
Glew quote about amount of OoOIreland2017/04/30 03:31 PM
Glew quote about amount of OoOMichael S2017/04/30 03:50 PM
Glew quote about amount of OoOIreland2017/05/01 09:21 AM
Glew quote about amount of OoOMaynard Handley2017/05/01 12:54 PM
Glew quote about amount of OoOMichael S2017/05/01 01:15 PM
Mill is optimized for frequent callsHenry S2017/04/21 01:27 AM
spillerRichardC2017/04/21 06:53 AM
spiller documentationRichardC2017/04/21 07:04 AM
spillerSymmetry2017/04/21 07:47 AM
spillerSymmetry2017/04/21 07:51 AM
Mill made more sense in 2003wumpus2017/04/21 06:59 AM
Mill made more sense in 2003wumpus2017/04/20 06:58 AM
Mill made more sense in 2003anon2017/04/18 07:02 PM
virtual method callsRichardC2017/04/19 07:50 AM
fractional bitsrwessel2017/04/17 01:14 AM
fractional bitsMichael S2017/04/17 11:50 AM
fractional bitsEugene Nalimov2017/04/17 07:25 PM
fractional bitsMegol2017/04/16 02:05 PM
fractional bitsdmcq2017/04/17 02:04 AM
fractional bitsGabriele Svelto2017/04/17 09:09 AM
fractional bitsMaynard Handley2017/04/17 10:53 AM
fractional bitsanon2017/04/17 01:29 PM
fractional bitsanon.12017/04/23 01:44 PM
fractional bitsMaynard Handley2017/04/23 02:19 PM
fractional bitsanon.12017/04/23 10:09 PM
fractional bitsMaynard Handley2017/04/24 12:07 AM
Excellent exampleHenry S2017/04/21 01:02 PM
Excellent exampleanon.12017/04/23 12:50 PM
I don't think that's the issueHenry S2017/04/25 09:22 AM
I don't think that's the issueanon.12017/04/25 07:45 PM
I don't think that's the issueMaynard Handley2017/04/25 09:59 PM
I don't think that's the issueanon.12017/04/26 09:47 PM
I don't think that's the issueMaynard Handley2017/04/27 09:59 AM
I don't think that's the issueanon.12017/04/27 09:32 PM
I don't think that's the issueMaynard Handley2017/04/27 10:24 PM
I don't think that's the issueanon.12017/04/28 06:51 AM
I don't think that's the issueanon.12017/04/28 07:20 AM
Hierarchical and distributedPaul A. Clayton2017/04/30 05:54 PM
Hierarchical and distributedanon.12017/05/01 09:25 AM
Hierarchical and distributedMaynard Handley2017/05/01 01:07 PM
fractional bitsanon2017/04/16 04:31 PM
OoO instruction windowPaul A. Clayton2017/04/17 05:43 PM
OoO instruction windowanon2017/04/17 06:57 PM
OoO instruction windowMaynard Handley2017/04/17 09:16 PM
OoO instruction windowanon2017/04/18 01:51 AM
OoO instruction windowwumpus2017/04/19 06:16 AM
Initiating post-return loads earlyPaul A. Clayton2017/04/18 07:39 AM
Initiating post-return loads earlyanon2017/04/18 05:28 PM
Software assisted prefetchingPaul A. Clayton2017/04/18 07:13 PM
Software assisted prefetchingMaynard Handley2017/04/18 09:04 PM
Software assisted prefetchingMichael S2017/04/19 12:49 AM
fractional bitsUngo2017/04/17 07:03 PM
fractional bitsMegol2017/04/16 01:33 PM
fractional bitsRichardC2017/04/16 01:43 PM
fractional bitsBrett2017/04/15 11:48 AM
RISC warsMichael S2017/04/15 12:04 PM
RISC warsBrett2017/04/15 03:18 PM
RISC warsdmcq2017/04/16 03:36 AM
RISC warsBrett2017/04/16 02:02 PM
RISC warsMaynard Handley2017/04/16 04:48 PM
RISC warsBrett2017/04/16 06:56 PM
RISC warsMaynard Handley2017/04/16 08:45 PM
RISC warsBrett2017/04/17 12:51 AM
RISC warsSimon Farnsworth2017/04/17 04:51 AM
RISC warsdmcq2017/04/17 05:24 AM
RISC warsBrett2017/04/22 01:36 PM
RISC warsMaynard Handley2017/04/22 02:14 PM
RISC warsBrett2017/04/22 04:54 PM
RISC warsMaynard Handley2017/04/22 08:17 PM
POWER8 - frequency, rename widthMichael S2017/04/23 12:47 AM
POWER8 - frequency, rename widthdmcq2017/04/23 09:01 AM
POWER8 - frequency, rename widthrwessel2017/04/23 09:10 AM
POWER8 - frequency, rename widthMaynard Handley2017/04/23 10:11 AM
POWER8 - frequency, rename widthTravis2017/04/23 02:31 PM
POWER8 - frequency, rename widthMaynard Handley2017/04/23 09:25 AM
POWER8 - frequency, rename widthMaynard Handley2017/04/23 10:30 AM
POWER8 is 2x(3+1), not 6+2anon2017/04/23 11:47 AM
POWER8 is 2x(3+1), not 6+2Travis2017/04/23 02:42 PM
exactly (NT)Michael S2017/04/23 03:33 PM
POWER8 is 2x(3+1), not 6+2anon2017/04/23 03:44 PM
Alpha 21264 (duplicated GPRs) was utter insane?! (I think not) (NT)Paul A. Clayton2017/04/23 05:58 PM
done for different reasonsanon2017/04/24 12:00 AM
Additive clustering/replication advantages?Paul A. Clayton2017/04/24 08:34 AM
Additive clustering/replication advantages?anon2017/04/25 04:43 PM
Additive clustering/replication advantages?anon22017/04/26 04:17 AM
Additive clustering/replication advantages?anon2017/04/26 05:13 AM
Additive clustering/replication advantages?anon22017/04/26 05:00 PM
Additive clustering/replication advantages?anon2017/04/27 03:08 AM
Additive clustering/replication advantages?anon22017/04/27 04:57 AM
Additive clustering/replication advantages?anon2017/04/27 07:05 AM
Additive clustering/replication advantages?Michael S2017/04/27 07:09 AM
Additive clustering/replication advantages?anon2017/04/27 08:21 AM
Additive clustering/replication advantages?anon22017/04/27 09:07 AM
Additive clustering/replication advantages?anon2017/04/27 10:54 AM
Additive clustering/replication advantages?anon22017/04/27 12:05 PM
Additive clustering/replication advantages?anon2017/04/27 01:52 PM
Additive clustering/replication advantages?anon22017/04/27 02:28 PM
Additive clustering/replication advantages?anon2017/04/28 04:14 AM
Additive clustering/replication advantages?anon22017/04/29 06:23 PM
POWER8 is 2x(3+1), not 6+2anon2017/04/23 09:12 PM
POWER8 is 2x(3+1), not 6+2anon2017/04/24 12:04 AM
POWER8 is 2x(3+1), not 6+2anon2017/04/24 01:26 AM
schizoMichael S2017/04/24 02:02 AM
no (NT)anon2017/04/24 02:10 AM
POWER8 is 2x(3+1), not 6+2Brett2017/04/24 08:55 PM
POWER8 is 2x(3+1), not 6+2anon2017/04/24 11:49 PM
incorrect POWER6 infoThu Nguyen2017/04/24 10:39 PM
incorrect POWER6 infoMichael S2017/04/24 11:59 PM
RISC warsBrett2017/04/23 03:35 PM
RISC warsBrett2017/04/24 12:25 AM
RISC warsBrett2017/04/24 09:33 PM
RISC warsanon2017/04/23 05:51 PM
Instruction Grouping is gone with POWER9Mark Roulo2017/04/24 03:39 PM
RISC warsMichael S2017/04/23 01:25 AM
RISC warsdmcq2017/04/25 08:06 AM
RISC warsdmcq2017/04/17 01:55 AM
Chains of single opcodes are stupidBrett2017/04/23 06:52 PM
Chains of single opcodes are stupidwumpus2017/04/25 06:48 AM
Chains of single opcodes are stupidHeikki kultala2017/04/26 12:42 AM
Chains of single opcodes are stupidBrett2017/05/05 11:36 PM
Chains of single opcodes are stupidBrett2017/05/06 11:29 PM
What 24-bit branches are you talking about?Heikki Kultala2017/05/07 08:44 PM
What 24-bit branches are you talking about?Brett2017/05/08 01:48 AM
What 24-bit branches are you talking about?anon2017/05/08 10:24 AM
What 24-bit branches are you talking about?Brett2017/05/09 10:33 PM
What 24-bit branches are you talking about?anon2017/05/10 03:30 AM
Branches and OS calls ...Mark Roulo2017/05/10 03:12 PM
Branches and OS calls ...Brett2017/05/10 07:40 PM
Code densityHeikki Kultala2017/05/07 08:03 PM
Code densityBrett2017/05/08 01:52 AM
Chains of single opcodes are stupidBrett2017/04/27 12:02 AM
Chains of single opcodes are stupidwumpus2017/04/27 07:06 AM
Chains of single opcodes are stupidanon2017/04/27 08:33 AM
Chains of single opcodes are stupidBrett2017/04/27 10:57 AM
Chains of single opcodes are stupidAdrian2017/04/27 11:21 AM
Chains of single opcodes are stupidBrett2017/04/28 10:47 PM
You sound like a fool (NT)anon22017/04/29 12:12 AM
You sound like a foolBrett2017/04/29 01:20 AM
You sound like a foolanon22017/04/29 03:03 AM
You sound like a foolBrett2017/04/29 11:24 PM
You sound like a foolMichael S2017/04/30 12:36 AM
You sound like a foolBrett2017/04/30 02:56 PM
You sound like a foolMichael S2017/04/30 04:14 PM
You sound like a foolBrett2017/04/30 05:03 PM
Laptop CPUsanon22017/04/30 06:10 PM
Chains of single opcodes are stupidAdrian2017/04/29 04:38 AM
Chains of single opcodes are stupidanon2017/04/27 11:34 AM
Chains of single opcodes are stupidBrett2017/04/27 11:35 PM
8088, 8086 and 16-bitnessHeikki Kultala2017/04/28 05:45 AM
8088, 8086 and 16-bitnessMichael S2017/04/28 06:10 AM
8088, 8086 and 16-bitnessBrett2017/04/28 08:57 AM
8088, 8086 and 16- and 20-bitnessHeikki kultala2017/04/28 10:56 AM
doubling momory capasity every 2 years I mean (NT)Heikki kultala2017/04/28 10:57 AM
8088, 8086 and 16- and 20-bitnessBrett2017/04/28 07:46 PM
8088, 8086 and 16- and 20-bitnessYuhong Bao2017/04/28 10:17 PM
8088, 8086 and 16-bitnessrwessel2017/04/28 12:21 PM
8088, 8086 and 16-bitnesswumpus2017/04/28 07:10 PM
8088, 8086 and 16-bitnessanon22017/04/29 12:02 AM
8088, 8086 and 16-bitnessSeni2017/04/29 04:59 AM
Chains of single opcodes are stupidBrett2017/05/05 10:56 PM
Chains of single opcodes are stupidwumpus2017/05/06 05:39 PM
Chains of single opcodes are stupidBrett2017/04/28 10:32 PM
patents, alpha etc.Heikki kultala2017/04/29 08:07 AM
patents, alpha etc.wumpus2017/04/29 10:23 AM
patents, alpha etc.Megol2017/05/10 07:27 AM
patents, alpha etc.rwessel2017/05/10 11:09 AM
patents, alpha etc.David Hess2017/05/10 06:18 PM
patents, alpha etc.Heikki Kultala2017/05/10 10:59 PM
patents, alpha etc.anonny mouse2017/05/11 12:30 AM
patents, alpha etc.Megol2017/05/11 04:49 AM
pipelining/OoOE and indirect addressing problemHeikki Kultala2017/05/11 06:42 AM
pipelining/OoOE and indirect addressing problemTEMLIB2017/05/11 11:18 AM
patents, alpha etc.rwessel2017/05/11 02:28 PM
patents, alpha etc.gallier22017/05/12 12:32 AM
patents, alpha etc.TEMLIB2017/05/11 11:22 AM
patents, alpha etc.Linus B Torvalds2017/05/12 08:25 AM
Chains of single opcodes are stupidBrett2017/04/29 11:49 PM
programming language of the futureCarlie Coats2017/05/11 05:58 AM
Fractional bits for instruction encodingdmcq2017/04/13 05:35 AM
Sounds like a FP counter with random rounding (NT)Paul A. Clayton2017/04/13 06:08 PM
Sounds like a FP counter with random roundingdmcq2017/04/14 11:35 AM
RISC *was* science, not religionMegol2017/04/12 02:13 PM
Mill load buffer and spillPaul A. Clayton2017/04/12 06:02 PM
RISC *was* science, not religionMichael S2017/04/09 02:51 AM
RISC *was* science, not religionanon2017/04/09 07:30 AM
ARM vs RISC religionHeikki Kultala2017/04/04 06:58 AM
religious vs atheist or SF Bay Area vs Rest of the World (NT)Michael S2017/04/04 07:25 AM
ARM vs RISC religionRichardC2017/04/04 07:44 AM
ARM vs RISC religionEtienne2017/04/04 08:22 AM
ARM vs RISC religionRichardC2017/04/04 08:39 AM
ARM vs RISC religionExophase2017/04/04 06:54 PM
that's a neat trick! (NT)RichardC2017/04/04 07:34 PM
ARM vs RISC religiondmcq2017/04/04 08:37 AM
ARM vs RISC religionwumpus2017/04/05 06:14 AM
RISC *was* science, not religionIreland2017/04/04 08:14 AM
RISC *was* science, not religionIreland2017/04/04 02:12 PM
RISC *was* science, not religionIreland2017/04/04 02:14 PM
RISC *was* science, not religionLinus Torvalds2017/04/04 10:10 AM
RISC *was* science, not religionMichael S2017/04/04 10:24 AM
RISC *was* science, not religionExophase2017/04/04 09:05 PM
RISC *was* science, not religionMichael S2017/04/05 12:58 AM
RISC *was* science, not religionExophase2017/04/05 10:07 AM
RISC *was* science, not religionMichael S2017/04/05 02:38 PM
Load delay slot new value after cache missPaul A. Clayton2017/04/06 09:29 AM
Load delay slot new value after cache missExophase2017/04/06 02:05 PM
unspcified behaviour load delay slot pessimalityHeikki Kultala2017/04/04 10:14 PM
RISC *was* science, not religionSimon Farnsworth2017/04/06 04:18 AM
RISC *was* science, not religionRichardC2017/04/06 08:54 AM
RISC *was* science, not religionSimon Farnsworth2017/04/06 10:51 AM
RISC *was* science, not religiondmcq2017/04/06 02:55 PM
RISC *was* science, not religionEtienne2017/04/07 03:36 AM
RISC *was* science, not religionRichardC2017/04/04 10:58 AM
RISC *was* science, not religionIreland2017/04/04 02:20 PM
RISC *was* science, not religionIreland2017/04/04 02:40 PM
RISC *was* science, not religionbakaneko2017/04/04 11:52 PM
RISC *was* science, not religionIreland2017/04/05 12:04 PM
RISC *was* science, not religiongallier22017/04/05 04:06 AM
RISC *was* science, not religionRichardC2017/04/05 08:14 AM
RISC *was* science, not religionSimon Farnsworth2017/04/05 10:01 AM
RISC *was* science, not religionSeni2017/04/05 11:26 AM
RISC *was* science, not religionDavid Hess2017/04/05 10:36 PM
RISC *was* science, not religionRichardC2017/04/06 11:32 AM
RISC *was* science, not religionExophase2017/04/06 02:07 PM
RISC *was* science, not religionLinus Torvalds2017/04/06 02:27 PM
Intel x86 registers to the rescue!Mark Roulo2017/04/06 02:45 PM
Intel x86 registers to the rescue!Linus Torvalds2017/04/06 03:25 PM
Intel x86 registers to the rescue!John Yates2017/04/06 04:51 PM
Intel x86 registers to the rescue!David Hess2017/04/08 05:49 AM
Intel x86 registers to the rescue!Ireland2017/04/08 03:47 PM
Intel x86 registers to the rescue!wumpus2017/04/08 05:51 PM
Intel x86 registers to the rescue!David Hess2017/04/09 02:57 PM
Memory laneJohn Yates2017/04/11 01:24 PM
Memory lanesomeone2017/04/12 05:27 AM
Memory laneJohn Yates2017/04/12 02:01 PM
Memory laneIreland2017/04/12 10:23 AM
Intel x86 registers to the rescue!dmcq2017/04/06 11:47 PM
RISC *was* science, not religionDavid Hess2017/04/08 05:16 AM
RISC *was* science, not religiongallier22017/04/05 10:49 PM
6502 = accumulator machine (NT)Wilco2017/04/06 02:22 AM
RISC *was* science, not religiongallier22017/04/05 11:12 PM
same difference ...RichardC2017/04/06 11:57 AM
RISC *was* science, not religionRonald Maas2017/04/04 08:04 PM
RISC *was* science, not religiondmcq2017/04/05 11:03 AM
RISC *was* science, not religionAdrian2017/04/05 01:24 PM
RISC *was* science, not religiongallier22017/04/05 11:33 PM
RISC *was* science, not religionRonald Maas2017/04/08 08:07 AM
RISC *was* science, not religionJohn Yates2017/04/05 02:39 PM
RISC *was* science, not religionRichardC2017/04/07 02:30 PM
RISC *was* science, not religionwumpus2017/04/08 07:41 AM
RISC *was* science, not religionLinus Torvalds2017/04/08 10:43 AM
RISC *was* science, not religionanon2017/04/08 07:53 PM
RISC *was* science, not religionLinus Torvalds2017/04/09 07:52 AM
VAX/VMS compatibilityRichardC2017/04/09 06:54 AM
VAX/VMS compatibilityIreland2017/04/09 07:19 AM
VAX/VMS compatibilityMichael S2017/04/09 07:20 AM
VAX/VMS compatibilityRichardC2017/04/09 07:32 AM
VAX/VMS compatibilitydmcq2017/04/09 07:47 AM
I suppose, you are only familiar with British mainfraimes (NT)Michael S2017/04/09 07:55 AM
I suppose, you are only familiar with British mainfraimesdmcq2017/04/09 04:12 PM
VAX/VMS compatibilityIreland2017/04/09 08:08 AM
VAX/VMS compatibilityrwessel2017/04/09 08:51 AM
VAX/VMS compatibilityIreland2017/04/09 11:35 AM
VAX/VMS compatibilityanon2017/04/09 05:24 PM
VAX/VMS compatibilityIreland2017/04/09 05:47 PM
VAX/VMS compatibilityanon2017/04/09 06:29 PM
VAX/VMS compatibilityIreland2017/04/09 06:43 PM
Ireland = AI botanonymou52017/04/10 04:21 AM
That joke is getting old (NT)Anon2017/04/11 12:23 AM
It isn't 100% a joke.Mark Roulo2017/04/11 06:13 AM
It isn't 100% a joke.Michael_S2017/04/11 09:19 AM
It isn't 100% a joke.Ireland2017/04/11 09:48 AM
It isn't 100% a joke.anonymou52017/04/12 08:40 PM
It isn't 100% a joke.Dan Downs2017/04/11 03:05 PM
Shaka, when the walls fell (NT)Darmok2017/04/11 11:19 PM
It isn't 100% a joke.Brendan2017/04/13 04:34 AM
Can Someone Fix "Greater Than/Less Than" Handling Bugs??Brendan2017/04/13 04:38 AM
6th decadeMichael S2017/04/13 05:34 AM
6th decadeIreland2017/04/13 09:17 AM
It isn't 100% a joke.Gabriele Svelto2017/04/15 07:14 AM
It isn't 100% a joke.dmcq2017/04/16 04:09 AM
It isn't 100% a joke.Brendan2017/04/16 02:01 PM
The less loquacious left it alone (NT)Anon2017/04/17 11:49 PM
To Wit, many here..John H2017/04/12 10:40 AM
To Wit, many here..Ireland2017/04/12 10:54 AM
VAX/VMS compatibilitydmcq2017/04/09 04:02 PM
VAX/VMS compatibilityIreland2017/04/09 04:19 PM
VAX/VMS compatibilityrwessel2017/04/09 09:20 PM
VAX/VMS compatibilitywumpus2017/04/10 05:14 AM
VAX/VMS compatibilityrwessel2017/04/10 07:10 AM
VAX/VMS compatibilitydmcq2017/04/10 09:11 AM
VAX/VMS compatibilityJohn Yates2017/04/12 06:42 PM
VAX/VMS compatibilityrwessel2017/04/12 08:19 PM
VAX/VMS compatibilityJohn Yates2017/04/12 08:41 PM
VAX/VMS development - thank you, JohnMichael S2017/04/13 03:54 AM
VAX/VMS development - thank you, JohnRob Thorpe2017/04/14 07:19 AM
VAX/VMS development - thank you, JohnJohn Yates2017/04/14 03:20 PM
VAX/VMS compatibilitydmcq2017/04/13 05:23 AM
RISC *was* science, not religionanon2017/04/08 10:04 AM
RISC *was* science, not religionIreland2017/04/08 11:01 AM
RISC *was* science, not religionwumpus2017/04/08 04:57 PM
RISC *was* science, not religionanon2017/04/09 09:49 AM
RISC *was* science, not religionRicardo B2017/04/09 03:15 PM
RISC *was* science, not religionanon2017/04/09 10:07 PM
RISC *was* science, not religionRicardo B2017/04/10 01:17 AM
RISC *was* science, not religionanon2017/04/10 08:01 AM
RISC *was* science, not religionRicardo B2017/04/10 10:27 AM
RISC *was* science, not religionanon2017/04/10 02:25 PM
RISC *was* science, not religionRicardo B2017/04/10 04:12 PM
RISC *was* science, not religionanon.12017/04/10 09:54 PM
RISC *was* science, not religionRicardo B2017/04/11 02:14 AM
RISC *was* science, not religiondmcq2017/04/11 02:44 AM
RISC *was* science, not religionanon.12017/04/11 08:03 AM
RISC *was* science, not religionWilco2017/04/11 01:04 PM
RISC *was* science, not religionanon2017/04/11 08:07 PM
RISC *was* science, not religionRicardo B2017/04/11 01:15 PM
RISC *was* science, not religionrwessel2017/04/11 04:38 PM
RISC *was* science, not religionanon2017/04/11 07:36 PM
RISC *was* science, not religionRicardo B2017/04/12 01:01 AM
RISC *was* science, not religionGabriele Svelto2017/04/12 01:38 AM
RISC *was* science, not religionTravis2017/04/12 11:20 AM
RISC *was* science, not religionanon.12017/04/11 09:54 PM
RISC *was* science, not religionRicardo B2017/04/12 12:52 AM
RISC *was* science, not religiondmcq2017/04/12 03:27 AM
RISC *was* science, not religionanon.12017/04/12 07:43 AM
RISC *was* science, not religionanon.12017/04/12 10:03 AM
RISC *was* science, not religionMichael S2017/04/11 01:32 PM
RISC *was* science, not religionanon.12017/04/11 09:45 PM
RISC *was* science, not religionMichael S2017/04/12 09:07 AM
RISC *was* science, not religiongpd2017/04/12 01:31 AM
RISC *was* science, not religionTravis2017/04/12 10:16 AM
RISC *was* science, not religionMichael S2017/04/12 10:27 AM
RISC *was* science, not religionTravis2017/04/12 11:02 AM
RISC *was* science, not religionMichael S2017/04/12 11:46 AM
RISC *was* science, not religionTravis2017/04/12 02:41 PM
RISC *was* science, not religionTravis2017/04/12 10:33 AM
RISC *was* science, not religionMichael S2017/04/12 11:56 AM
RISC *was* science, not religionTravis2017/04/12 03:22 PM
RISC *was* science, not religionMichael S2017/04/11 11:08 AM
RISC *was* science, not religionanon2017/04/11 01:10 AM
RISC *was* science, not religionRicardo B2017/04/11 02:28 AM
RISC *was* science, not religionanon2017/04/11 03:46 AM
RISC *was* science, not religionmatthew2017/04/11 07:59 AM
RISC *was* science, not religionanon2017/04/11 12:28 PM
RISC *was* science, not religionMichael S2017/04/11 10:41 AM
RISC *was* science, not religionanon.12017/04/10 07:03 PM
RISC *was* science, not religionRicardo B2017/04/11 02:47 AM
RISC *was* science, not religionbakaneko2017/04/03 10:45 PM
RISC *was* science, not religionMichael S2017/04/04 12:45 AM
RISC *was* science, not religionIreland2017/04/04 08:30 AM
RISC *was* science, not religiondmcq2017/04/04 08:43 AM
RISC *was* science, not religionDavid Hess2017/04/05 01:18 AM
RISC *was* science, not religionMichael S2017/04/05 03:02 AM
RISC *was* science, not religionDavid Hess2017/04/05 12:54 AM
RISC *was* science, not religionRichardC2017/04/05 03:31 AM
ARM solution and MIPS condition evaluation?Heikki Kultala2017/04/05 04:23 AM
ARM solution and MIPS condition evaluation?dmcq2017/04/05 06:34 AM
MIPS condition evaluation?Heikki Kultala2017/04/05 07:28 AM
MIPS condition evaluation?Michael S2017/04/05 09:28 AM
MIPS condition evaluation?Heikki Kultala2017/04/05 09:55 AM
MIPS condition evaluation?Michael S2017/04/05 11:12 AM
MIPS condition evaluation?Heikki Kultala2017/04/05 11:54 AM
MIPS condition evaluation?dmcq2017/04/05 12:02 PM
MIPS condition evaluation?Heikki Kultala2017/04/05 12:03 PM
ARM solution and MIPS condition evaluation?RichardC2017/04/05 08:18 AM
ARM solution and MIPS condition evaluation?Linus Torvalds2017/04/05 10:20 AM
ARM solution and MIPS condition evaluation?RichardC2017/04/05 12:23 PM
ARM solution and MIPS condition evaluation?Linus Torvalds2017/04/05 04:51 PM
ARM solution and MIPS condition evaluation?RichardC2017/04/05 08:06 PM
TransputerRichardC2017/04/06 04:20 AM
ARM solution and MIPS condition evaluation?Linus Torvalds2017/04/06 07:54 AM
ARM solution and MIPS condition evaluation?RichardC2017/04/06 10:14 AM
ARM solution and MIPS condition evaluation?Linus Torvalds2017/04/06 10:40 AM
ARM solution and MIPS condition evaluation?RichardC2017/04/06 11:01 AM
your theoryRichardC2017/04/06 12:49 PM
your theoryLinus Torvalds2017/04/06 01:39 PM
your theoryLinus Torvalds2017/04/06 02:04 PM
your theoryIreland2017/04/06 02:48 PM
Integrators of RISC cpu's interested only in software app salesIreland2017/04/06 04:11 PM
cheap machines with GUIsRichardC2017/04/07 03:40 AM
compatibility and evolutionary strategyRichardC2017/04/07 05:27 AM
68K clones?Michael S2017/04/07 05:40 AM
68K clones?Yuhong Bao2017/04/07 06:54 AM
Apollo core ...Mark Roulo2017/04/07 09:28 AM
68K clones?Ronald Maas2017/04/07 05:07 PM
68K clones?Per Hesselgren2017/04/08 12:05 AM
68K clones?Per Hesselgren2017/04/08 12:06 AM
68K clones?Michael S2017/04/08 11:10 AM
compatibility and evolutionary strategyIreland2017/04/07 08:33 AM
compatibility and evolutionary strategyIreland2017/04/07 08:50 AM
high-margin productsRichardC2017/04/07 09:16 AM
high-margin productsIreland2017/04/07 01:53 PM
high-margin productswumpus2017/04/08 06:45 PM
high-margin productsRichardC2017/04/09 05:06 AM
high-margin productsMichael S2017/04/09 05:26 AM
high-margin productsIreland2017/04/09 06:13 AM
high-margin productswumpus2017/04/09 09:01 AM
user-visible ISA's still evolvingRichardC2017/04/09 07:09 AM
user-visible ISA's still evolvingIreland2017/04/09 02:08 PM
Economics and doing a MIPS, SGI or 3dfx startup today . . . Ireland2017/04/09 07:08 AM
Economics and doing a MIPS, SGI or 3dfx startup today . . . bakaneko2017/04/09 09:45 AM
Economics and doing a MIPS, SGI or 3dfx startup today . . . Ireland2017/04/09 12:32 PM
your theoryRichardC2017/04/06 03:57 PM
your theoryIreland2017/04/06 04:29 PM
your theoryIreland2017/04/06 04:45 PM
x86 ISA license historyRichardC2017/04/06 04:31 PM
x86 ISA license historywumpus2017/04/07 06:35 AM
x86 ISA license historyRichardC2017/04/07 08:26 AM
370 on 68KMatt Sayler2017/04/06 04:38 PM
370 on 68KDavid Hess2017/04/08 09:18 AM
your theoryLinus Torvalds2017/04/06 06:20 PM
your theoryRichardC2017/04/06 07:34 PM
Intel's clone warsRichardC2017/04/06 07:42 PM
your theoryIreland2017/04/07 08:05 AM
your theoryrwessel2017/04/06 09:53 PM
your theorygallier22017/04/07 01:13 AM
your theorygallier22017/04/07 01:37 AM
your theoryMichael S2017/04/07 04:54 AM
your theorygallier22017/04/07 08:57 AM
your theoryDavid Hess2017/04/08 09:26 AM
your theoryYuhong Bao2017/04/08 09:28 AM
your theorygallier22017/04/09 04:38 AM
your theoryMichael S2017/04/09 05:08 AM
your theoryrwessel2017/04/09 09:04 AM
your theoryDavid Hess2017/04/09 03:46 PM
your theoryrwessel2017/04/09 07:58 PM
your theoryDavid Hess2017/04/09 03:23 PM
your theoryRichardC2017/04/09 07:16 AM
your theoryDavid Hess2017/04/09 03:58 PM
Positive point about 80286Michael S2017/04/07 05:31 AM
Positive point about 80286gallier22017/04/07 09:00 AM
Positive point about 80286Yuhong Bao2017/04/07 01:43 PM
Positive point about 80286Per Hesselgren2017/04/08 12:16 AM
Positive point about 80286David Hess2017/04/08 09:49 AM
Positive point about 80286gallier22017/04/09 04:44 AM
Positive point about 80286Ireland2017/04/09 05:35 AM
Positive point about 80286gallier22017/04/09 06:18 AM
Positive point about 80286Ireland2017/04/09 06:30 AM
Positive point about 80286gallier22017/04/09 09:43 AM
Positive point about 80286David Hess2017/04/09 04:19 PM
Positive point about 80286Ireland2017/04/09 04:24 PM
Positive point about 80286David Hess2017/04/09 05:01 PM
Positive point about 80286Ireland2017/04/09 05:15 PM
Positive point about 80286 and MotorolaPer Hesselgren2017/04/09 11:22 PM
Positive point about 80286 and MotorolaPer Hesselgren2017/04/10 12:01 AM
Positive point about 80286 and MotorolaPer Hesselgren2017/04/10 12:39 PM
Positive point about 80286 and MotorolaPer Hesselgren2017/04/18 08:14 AM
Positive point about 80286gallier22017/04/09 11:26 PM
Positive point about 80286Michael_S2017/04/10 02:21 AM
Positive point about 80286David Hess2017/04/09 04:11 PM
Positive point about 80286gallier22017/04/10 12:15 AM
Positive point about 80286gallier22017/04/10 12:20 AM
Positive point about 80286rwessel2017/04/09 09:12 AM
Positive point about 80286gallier22017/04/09 10:38 AM
Positive point about 80286Ireland2017/04/09 11:17 AM
Positive point about 80286David Hess2017/04/09 04:40 PM
Positive point about 80286Ireland2017/04/09 04:48 PM
Positive point about 80286rwessel2017/04/09 10:05 PM
Positive point about 80286wumpus2017/04/10 05:31 AM
Positive point about 80286rwessel2017/04/10 06:37 AM
Positive point about 80286David Hess2017/04/10 08:53 AM
Positive point about 80286David Hess2017/04/09 04:51 PM
Positive point about 80286wumpus2017/04/11 05:41 AM
Positive point about 80286gallier22017/04/12 03:20 AM
Positive point about 80286Yuhong Bao2017/04/17 12:14 AM
Positive point about 80286David Hess2017/04/17 01:37 AM
Positive point about 80286Joe Hodge2017/04/17 05:54 PM
Positive point about 80286David Hess2017/04/09 04:05 PM
Positive point about 80286Ireland2017/04/09 04:13 PM
Positive point about 80286wumpus2017/04/09 04:22 PM
Positive point about 80286Ireland2017/04/09 04:43 PM
Positive point about 80286Ireland2017/04/09 04:59 PM
Positive point about 80286wumpus2017/04/09 04:17 PM
Positive point about 80286Ireland2017/04/09 04:20 PM
your theorydmcq2017/04/07 12:04 AM
your theoryGabriele Svelto2017/04/09 12:47 PM
your theoryIreland2017/04/09 04:53 PM
your theoryrwessel2017/04/09 10:24 PM
ARM solution and MIPS condition evaluation?Doug S2017/04/07 10:24 AM
ARM solution and MIPS condition evaluation?Linus Torvalds2017/04/07 10:50 AM
ARM solution and MIPS condition evaluation?Doug S2017/04/10 08:58 PM
ARM solution and MIPS condition evaluation?Tim McCaffrey2017/04/06 05:32 PM
ARM solution and MIPS condition evaluation?Doug S2017/04/05 10:58 PM
Are you sure about orders of magnitude? (NT)Michael S2017/04/06 02:24 AM
ARM solution and MIPS condition evaluation?Tim McCaffrey2017/04/06 05:21 PM
ARM solution and MIPS condition evaluation?somebody2017/04/06 08:41 AM
ARM solution and MIPS condition evaluation?Linus Torvalds2017/04/06 11:01 AM
ARM solution and MIPS condition evaluation?Wilco2017/04/06 06:17 PM
ARM solution and MIPS condition evaluation?Linus Torvalds2017/04/07 10:35 AM
ARM solution and MIPS condition evaluation?Linus Torvalds2017/04/07 11:20 AM
ARM solution and MIPS condition evaluation?Exophase2017/04/07 12:22 PM
ARM solution and MIPS condition evaluation?Linus Torvalds2017/04/08 12:32 AM
Software FP vs trap emulationWilco2017/04/08 04:20 AM
Software FP vs trap emulationRonald Maas2017/04/08 07:45 AM
Software FP vs trap emulationdmcq2017/04/08 09:29 AM
Software FP vs trap emulationdmcq2017/04/08 09:44 AM
Software FP vs trap emulationWilco2017/04/08 04:24 PM
Software FP vs trap emulationLinus Torvalds2017/04/08 09:52 AM
Software FP vs trap emulationIreland2017/04/08 10:46 AM
Software FP vs trap emulationMichael S2017/04/08 12:23 PM
Software FP vs trap emulationLinus Torvalds2017/04/08 02:38 PM
Software FP vs trap emulationMichael S2017/04/08 03:23 PM
Software FP vs trap emulation@2017/04/08 05:17 PM
Software FP vs trap emulationLinus Torvalds2017/04/09 07:59 AM
Software FP vs trap emulationIreland2017/04/09 08:20 AM
Software FP vs trap emulationIreland2017/04/09 08:35 AM
Software FP vs trap emulationrwessel2017/04/09 09:27 AM
Software FP vs trap emulationIreland2017/04/09 12:49 PM
Software FP vs trap emulation@2017/04/09 10:59 AM
Software FP vs trap emulationMichael S2017/04/08 11:46 AM
Software FP vs trap emulationWilco2017/04/08 04:01 PM
Software FP vs trap emulationBrett2017/04/08 10:30 PM
Software FP vs trap emulationmatthew2017/04/09 12:14 AM
Software FP vs trap emulationWilco2017/04/09 06:10 AM
Acorn vs DECRichardC2017/04/09 07:27 AM
ARM solution and MIPS condition evaluation?Exophase2017/04/09 12:02 PM
ARM solution and MIPS condition evaluation?Wilco2017/04/09 01:52 PM
ARM solution and MIPS condition evaluation?Exophase2017/04/09 05:16 PM
ARM solution and MIPS condition evaluation?Wilco2017/04/10 12:40 AM
ARM solution and MIPS condition evaluation?Exophase2017/04/10 12:00 PM
ARM solution and MIPS condition evaluation?Wilco2017/04/10 03:19 PM
ARM solution and MIPS condition evaluation?Ireland2017/04/07 04:34 PM
RISC *was* science, not religionDavid Hess2017/04/05 11:24 PM
RISC *was* science, not religionIreland2017/04/06 08:54 AM
RISC *was* science, not religionIreland2017/04/05 12:23 PM
CISC religion?wumpus2017/04/08 08:49 AM
CISC religion?Ireland2017/04/08 12:24 PM
CISC religion?Ireland2017/04/08 12:39 PM
Alan Turing Ireland2017/04/08 04:31 PM
Alan Turing rwessel2017/04/08 08:52 PM
Alan Turing Ireland2017/04/09 04:35 AM
CISC religion?wumpus2017/04/08 06:19 PM
narrow vs wide skillsetsRichardC2017/04/08 06:42 PM
CISC religion?rwessel2017/04/08 08:33 PM
CISC religion?wumpus2017/04/09 04:10 PM
CISC religion?David Hess2017/04/09 06:56 PM
CISC religion?rwessel2017/04/09 11:25 PM
CISC religion?RichardC2017/04/08 02:44 PM
CISC religion?Michael S2017/04/08 03:47 PM
CISC religion?Michael S2017/04/08 03:52 PM
CISC religion?Ireland2017/04/08 04:16 PM
CISC religion?Michael S2017/04/08 04:26 PM
CISC religion?Ireland2017/04/08 04:41 PM
CISC religion?wumpus2017/04/08 07:04 PM
OT - faster RAMMichael S2017/04/09 04:26 AM
CISC religion?rwessel2017/04/08 09:10 PM
CISC religion?rwessel2017/04/08 09:10 PM
gone parallel now ...RichardC2017/04/08 06:15 PM
CISC religion?gallier22017/04/09 05:47 AM
fascinating link, thanks! (NT)RichardC2017/04/09 08:46 AM
CISC religion?Ricardo B2017/04/10 04:55 AM
CISC religion?anon2017/04/10 08:49 AM
CISC religion?Travis2017/04/10 10:30 AM
CISC religion?Travis2017/04/10 10:32 AM
CISC religion?anon2017/04/10 01:12 PM
CISC religion?Travis2017/04/10 06:41 PM
CISC religion?Michael_S2017/04/11 09:44 AM
CISC religion?Ricardo B2017/04/10 03:01 PM
CISC religion?Michael_S2017/04/11 09:56 AM
CISC religion?Ricardo B2017/04/11 12:27 PM
CISC religion?Wilco2017/04/11 12:45 PM
CISC religion?Michael S2017/04/11 01:07 PM
CISC religion?Ricardo B2017/04/11 03:32 PM
CISC religion?Ricardo B2017/04/10 03:24 PM
CISC religion?dmcq2017/04/10 01:17 PM
CISC religion?Ricardo B2017/04/10 04:16 PM
CISC religion?Seni2017/04/09 03:06 AM
CISC religion?Ireland2017/04/09 04:40 AM
CISC religion?wumpus2017/04/09 09:08 AM
yes, except ARM and SPARC lacked cacheRichardC2017/04/09 04:50 AM
yes, except ARM and SPARC lacked cacheSeni2017/04/09 05:19 AM
yes, except ARM and SPARC lacked cacheRichardC2017/04/09 07:47 AM
minimal microcodeRichardC2017/04/09 08:33 AM
minimal microcodeSeni2017/04/09 09:02 AM
interesting, that makes sense (NT)RichardC2017/04/09 01:45 PM
yes, except ARM and SPARC lacked cacheanon2017/04/09 07:57 PM
yes, except ARM and SPARC lacked cacheRichardC2017/04/10 05:18 AM
yes, except ARM and SPARC lacked cacheSeni2017/04/10 02:51 PM
yes, except ARM and SPARC lacked cacheWilco2017/04/11 01:56 AM
yes, except ARM and SPARC lacked cachedmcq2017/04/11 02:06 AM
no, ARM's 42 rows x 36 bits = 189 bytes (NT)RichardC2017/04/11 07:11 AM
no, ARM's 42 rows x 36 bits = 189 bytesdmcq2017/04/12 03:42 AM
yes, except ARM and SPARC lacked cacheSeni2017/04/11 11:27 AM
yes, except ARM and SPARC lacked cacherwessel2017/04/11 05:02 PM
yes, except ARM and SPARC lacked cacheSeni2017/04/11 09:27 PM
yes, except ARM and SPARC lacked cacheRichardC2017/04/12 10:06 AM
yes, except ARM and SPARC lacked cacheSeni2017/04/12 11:47 AM
yes, except ARM and SPARC lacked cacheWilco2017/04/12 12:38 PM
not the normal usageRichardC2017/04/12 06:58 PM
yes, except ARM and SPARC lacked cacherwessel2017/04/12 08:40 PM
yes, except ARM and SPARC lacked cachedmcq2017/04/12 01:19 PM
yes, except ARM and SPARC lacked cacherwessel2017/04/12 08:49 PM
yes, except ARM and SPARC lacked cachedmcq2017/04/13 02:44 AM
yes, except ARM and SPARC lacked cacheanon2017/04/12 07:06 PM
yes, except ARM and SPARC lacked cachewumpus2017/04/10 05:37 AM
Apple confirms that they are ditching Imagination within two yearsAnon2017/04/03 01:36 AM
Apple confirms that they are ditching Imagination within two yearsDoug S2017/04/03 11:56 AM
Or Samsung buys them, develops their own GPU, and uses the patents in the next lawsuit (NT)Anon2017/04/03 12:26 PM
Or Samsung buys them, develops their own GPU, and uses the patents in the next lawsuit Michael S2017/04/03 01:33 PM
Or ARM buys them, and gets any money they can from their IP and customersdmcq2017/04/04 08:55 AM
IMGTEC stock has crashed already.VertexMaster2017/04/03 04:33 AM
IMGTEC stock has crashed already.Andreas2017/04/03 06:33 AM
IMGTEC stock has crashed already.Exophase2017/04/03 08:43 AM
IMGTEC stock has crashed already.Doug S2017/04/03 11:51 AM
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