Moore's law left other levers partially tapped

By: someone (someone.delete@this.somewhere.com), April 21, 2017 5:31 am
Room: Moderated Discussions
Mitch Hayenga (no.delete@this.thanks.com) on April 20, 2017 10:13 pm wrote:
> someone (someone.delete@this.somewhere.com) on April 20, 2017 9:53 pm wrote:
> > Mitch Hayenga (no.delete@this.thanks.com) on April 20, 2017 9:03 pm wrote:
> > > someone (someone.delete@this.somewhere.com) on April 19, 2017 6:31 am wrote:
> > > > Foo_ (foo.delete@this.nomail.com) on April 19, 2017 1:20 am wrote:
> > > > > The end of Moore's law seems very likely in the 5 to 15 years timeframe now.
> > > > > Are there any resources studying the macro-economic consequences thereof?
> > > > >
> > > > > I can try to infer a few. The hardware industry will switch to a model yielding 20%+ improvements
> > > > > per year on various metrics to model yielding a mere 2% per year (ballpark figures, of course).
> > > >
> > > > I think this is too pessimistic.
> > > >
> > > > Even if you froze process development/improvement totally the industry could probably
> > > > coast with >2% average annual improvement from design optimisation, circuit improvements,
> > > > better understanding product usage, manufacturability headroom etc for at least a decade.
> > > > When you are on a product development treadmill tied to process shrinks an awful lot of
> > > > potential is left on the cutting room floor so to speak to meet schedule.
> > > >
> > > > In practice, in such a world product improvements would be lumpier than 2% and much less
> > > > frequent than annual because no one will burn mask set and silicon verification costs
> > > > every year for just 2%.
> > > >
> > > > Of course processes will continue to improve, just not as fast and in the same ways as
> > > > in the past. Less frequent process changes means longer time for designers to fully use
> > > > the potential of each process. I think we clearly see that with Intel's 14 nm.
> > >
> > >
> > > Eh, performance gains have been pretty paltry even with some scaling. Recently I made this
> > > graph mining data from spec.org. I took the highest SPECINT score (not rate) for each calendar
> > > year since the Pentium Pro. Converted between SPEC 95/2000/2006 by using a conversion ratio
> > > (assumed highest SPEC2000 score in 2006 == highest SPEC2k6 score in 2006).
> > >
> > > SPECINT Performance Scaling
> > >
> > > Even with scaling, we've only been getting 5%/yr on SPECINT for the last 7 years. The previous 35%/yr
> > > fits nicely with the old rule of thumb that performance doubled every 2 years (rule of 72).
> >
> > Why don't you plot MPU socket power growth alongside SPECINT growth.
> >
> > I suspect the break point of slope in the latter corresponds well with the
> > inflection of the former. :-)
> >
> >
>
> That would be a cool graph, but I can't get the data to fit it. Too many old Intel
> parts had 130-150W TDPs vs newer ones like Skylake (i7-6700K 91W TDP).

That was kind of my point.

A lot of process tech shrink benefits of the last decade have gone into bringing socket
power growth under control and in most cases on a negative trend (even while raising
the number of CPUs per device, and in the case of client silicon, integrating ever more
powerful GPUs!) rather than simply driving single thread performance ever higher.

Much of the SPECInt growth of the 90s was largely derived from allowing single core
device socket power to grow from ~10W to over 100W. That trend was unsustainable
for a number of practical and technical reasons.

The break in SPECint growth trend you show was due more to sanity final prevailing in
capping and reversing socket power growth rather than a breakdown in Moore's Law.

Try plotting SPECint_rate per socket growth over the same time span. Moore's law has
been in fine health over the past decade thank you very much.

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