Cell height, Vt control

By: AM (myname4rwt.delete@this.jee-male.com), June 15, 2018 10:54 am
Room: Moderated Discussions
Hans de Vries (nospam.delete@this.thanks.com) on June 14, 2018 1:31 pm wrote:
> AM (myname4rwt.delete@this.jee-male.com) on June 14, 2018 10:52 am wrote:
> > Hans de Vries (nospam.delete@this.thanks.com) on June 13, 2018 2:50 pm wrote:
> > > AM (myname4rwt.delete@this.jee-male.com) on June 13, 2018 9:10 am wrote:
> > > > Techisights is fast once again, now with Intel's 10nm process.
> > > >
> > > > One truly shocking bit is the use of Ru -- something Intel never mentioned anywhere, and not only wrt
> > > > 10nm process afaik (if, by chance, you saw Intel talk about Ru, do mention it in the comments).
> > > >
> > > > Another interesting bit is 6.2-Track lib -- something I have difficulty making sense of, even considering
> > > > the curious 36/34 nm mismatch b/w mmp and fp in Intel's 10nm. E.g. Intel's lib they used for their 100
> > > > Mtr/mm² density calculations is 7.(5)-track by mmp, but exactly 8-"track" by fp. With 6.2 tracks, I
> > > > don't see how it could possibly convert to a whole number. A mismeasurement or a typo perhaps?
> > > >
> > > > http://techinsights.com/technology-intelligence/overview/latest-reports/intel-10-nm-logic-process/
> > >
> > > intel 10nm versus GF 7nm
> > >
> > > That Intel changed from 7.5 tracks to 6 tracks halfway the
> > > design could be deduced from the metal pitches alone.
> > >
> > > See my image from December 2017, I re-engineerd the layout using the pitch numbers only.
> > >
> > > That also explained the need for contact-over-gate: Because they
> > > lost tracks they had to come up with extra contact options.
> > >
> > > Hans
> >
> > Very interesting, Hans, thanks, I haven't seen this. However, looking at figures,
> > rounded values of M2P for 7.5T and 6T cells would be 53nm for 14nm (Intel quotes
> > 52nm) and 45nm for 10nm (Intel quotes 44nm). Do you have any explanation?
> >
> > I also spotted a quote of your comment and unfortunately
> > can't find the source, but it looks very interesting,
> > I'd like a look. Could you direct me to the source or writeup on your site (there's no link to it)? Thanks.
>
> The Track-Count-Number 6.2 comes from dividing the given cell height (272 nm) by the M2 metal pitch
> (44 nm). The power and ground lines can be wider so you can get any (non-integer) track number.

Looks like Intel might have misquoted metal pitches after all -- back in 2014 Dick measured 14nm m2p at 54 nm (whereas Intel quoted 52nm), so taking Intel's 399nm cell hight as a reference, we likely have 53nm pitch for the 7.5T-high cell. Perhaps the exact same story is with 10nm m2p, and the real figure is not 44nm as quoted by Intel, but 45nm and *exactly* 6T-high cells? What do you think? It somewhat puts in question Techinsights' findings, but at least it makes a bit more sense that way.

> The use of Cobalt or Ruthenium to encapsulate Copper interconnect improves
> electromigration so much that the power and ground lines can be significantly
> thinner which reduces the cell height, and thus the track-number-count.

But isn't it intracell routing considerations which are both major concern and determining factor there?

> Personally I suspect that Intel's 10nm problems have to do with the transistor work functions
> defined by surface electrostatics, the metal combinations used in the HKMG gates. This replaces
> the use of doping to define the transistor's work function. The physical volume of the gates
> has become so small that the very few doping atoms vary a lot from gate to gate.
>
> The companies that followed the Gate-First HKMG approach had to do an enormous amount of research
> taking years to test 'hundredths of thousands' of combinations and may now have an advantage.
>
> The post you mention:
>
> SemiWiki Post 1
>
> SemiWiki Post 2

Thanks a lot for the links.

Hans, I'm not sure I follow your comment re. gate-first: both TSMC and GF switched to gate-last, the former at 28nm iirc, the latter at 14nm (or was it 20? not sure I recall correctly). As for Vt control, I agree, undoped channel looks like the better way to go, and Intel being a step behind TSMC/GF with that should rather enjoy latecomer's advantage wrt learning. Besides, they are doing nothing extreme -- 2 process flavors with 4 or 6 wf metals (GF uses 8 in 7nm).

There's actually one curious thing here which made me wonder why they switched to wf metals when their 10nm tech was disclosed -- their reportedly *awesome* results with Vt control in 14nm with channel doping, putting Vt variation back to what they had at 90nm or 65nm (or something -- writing from memory, might be a bit wrong with nodes).

I still wonder what was the main enabler of that. Could it be something about FinFET (full depletion perhaps) that somehow enables it? Or some truly breakthrough doping technique they invented and yet scrapped it in favor of wf-metal Vt control? If you happen to know, I'm definitely interested!
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Intel's 10nm process got analyzed with a shocking disclosureAM2018/06/13 09:10 AM
  Intel's 10nm process got analyzed with a shocking disclosureHans de Vries2018/06/13 02:50 PM
    Intel's 10nm process got analyzed with a shocking disclosureAM2018/06/14 10:52 AM
      Intel's 10nm process got analyzed with a shocking disclosureHans de Vries2018/06/14 01:31 PM
        Cell height, Vt controlAM2018/06/15 10:54 AM
    Intel's 10nm process got analyzed with a shocking disclosurePhill2018/06/14 07:17 PM
  possible explinationsomeone2018/06/15 11:38 AM
    possible explinationAM2018/06/16 11:01 AM
      possible explinationanon2018/06/16 05:17 PM
        enough confusionAM2018/06/18 10:56 AM
          enough confusionHans de Vries2018/06/18 05:54 PM
            enough confusionHans de Vries2018/06/18 06:06 PM
              enough confusionanon2018/06/19 08:29 AM
              cell heightAM2018/06/19 08:51 AM
                cell heightHans de Vries2018/06/19 01:10 PM
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