Intel's 10nm IITC paper and AMAT's pubs provide some clues

By: AM (, June 22, 2018 11:50 am
Room: Moderated Discussions
Thanks to a forum member, I managed to take a look at Intel's IITC paper, and it contains a few interesting clues. In case you didn't read my Intel 10nm writeup I suggest you should read it before proceeding.

But first, there is not a single word in there about ruthenium that Techinsights found in i3-8121U.

The paper talks about increased EM resistance, all right, but according to their own graph, Co caps -- what GF are doing and, btw, what Intel says they're doing too -- deliver 1000x advantage, and pure Co is 50x on top of that, which renders it *unnecessary*. Sure, 50000x is better than 1000x, but 1000x is a honking huge overkill -- there's simply no way to take full advantage of that, so why seek more?

Another important bit is "At the short range routing distances typical of M0 and M1, the intrinsic resistance penalty of cobalt (vs. copper) is negligible, especially when the true copper volume at sub-40nm pitches is considered. Additionally, mobility of cobalt in low K dielectric is low that permits a simple titanium-based liner, thereby minimizing interlayer via resistance at these high via count layers."

Quite frankly, it looks like they are not even trying too hard to conceal that they found that Co indeed loses to Cu in lines, but at least they succeeded with vias. This is actually consistent with recent results from
a) imec -- Co loses to Cu for lines all the way to 3 nm (300 nm² cross-section, 12nm linewidth), but wins for vias,
b) AMAT -- in their recent launch of cobalt suite they gave specific resistance figures for replacement of W contacts (also a vertical struc, where cross-section gap between Cu(W) and Co due to thinner liner is apparently significant enough to justify the switch), but were very shy of claiming any win for lines, despite their ongoing advocacy of CuCo stack (coincidentally, exactly like what Intel is doing).

One thing I don't really appreciate about AMAT is not their advocacy of cobalt per se (the reasons are obvious), but the fact they they are not entirely straightforward in this regard. Not downright dishonest, only somewhat misleading -- a quick glance at their pictures easily creates a different impression, you have to closely read the "fine print", and even that will not necessarily clear out everything.

For example, take a look at Jonathan Bakke's recent blog post, namely Fig. 3: what's your impression from a quick glance concerning the impact of cobalt on performance? It's a win, right?

But diving in the fine print below we discover that "While copper as a bulk metal has a lower resistance than cobalt, there is a crossover point in the 10–15nm range where cobalt interconnects have lower resistance than copper."

But 10-15nm CD is probably several nodes away from now (min metal pitch for 7nm processes and Intel's 10nm is 36-40nm, take a half for CD, and how mmp will *actually* scale past 7nm is anyone's guess). But AMAT's estimation for the CD at which we have resistivity crossover is consistent with above-mentioned recent research results published by imec, who estimate 12nm CDs correspond to 3nm node.

Going further, we read "Also, as mentioned earlier, cobalt works with thinner barriers than copper and as a result, the vertical resistance in the via is lower for cobalt interconnects. For these reasons, cobalt helps unlock the full potential of transistors at the 7nm foundry node and below."

Again consistent with imec's research, but unless you're in the loop for this sort of stuff, you simply won't be able to read the hidden message here, which is "cobalt wins for vias" means in fact "cobalt loses for lines".

Right next we read "Finally, we have demonstrated the value of cobalt using EDA simulations of a 5-stage ring oscillator circuit. We showed that for a range of CDs simulated, the performance of the circuit with cobalt was better than for tungsten. In fact, this benefit for cobalt increases as CDs shrink, with a highly significant improvement of up to 15 percent in chip performance."

Okay, so finally we have something that looks like cobalt finally drives a nail in the non-cobalt interconnect's coffin? Not in the copper coffin though, but at least in the tungsten used for contacts, right?

Well, let's take a closer look at the picture (Fig. 3). First, the 15% advantage corresponds to 6nm CD, or min metal pitch of about 12nm. Which node is it, how far from now? Well, 7nm (Intel 10nm) process have min metal pitch of 36-40nm or about 20nm CD, and the win for that CD is about 2% according to their chart.

But if you think surprizes are over at this point, you're wrong. Let's go to fine print on the picture now: "compares cobalt with tungsten transistor contacts. Excludes via and M1 effects".

Why? Because Co line resistance is in fact higher than Cu line resistance down to about 12nm CD (imec) or 10-15nm (AMAT)! I must say I'm surprized they decided to exclude vias for the comparison, but that's probably because their impact on total delay is simply too small to bother including. So what happens to RO stage delay if we were to factor in vias and lines? Make a wild guess.

Now let's take a look at Jonathan Bakke's recent interview:
"As far as pure material cost is concerned, cobalt is three times more expensive than tungsten, but it remains inconvenient for us to comment on the actual cost that also involves the cost of collaborative R&D with customers."

Well, that's quite fair Jonathan, but in my opinion it would be more fair if you also pointed out that cobalt is 12x-13x more expensive than copper.

So as far as resistance alone is concerned, by all accounts now -- including Intel's and AMAT's own -- Co interconnect (vias + lines) at 36-40nm mmp is a one step forward, two steps backwards kind of thing. And not even two, but in fact many -- if you consider the ratio of line length to via height.

But probably what's more important here, the authors of Intel's IITC paper don't even touch issues which, in my strong opinion, are the core reasons for their neverendig problems -- mechanicals (fatigue failure of Co interconnect) and thermal gasket effect (more severe hotspotting due to 4x worse thermal conductivity of Co).

Contributing to these problems is intrinsic difficulty with
a) modeling, as we're talking about fatigue failure, which is still a grand challenge except in trivial cases) and
b) mere detection of this bug, let alone finding a cure for it.

Some people mentioned COAG and SAQP as the reason of Intel's problems. They can be blamed, but in a somewhat special sense -- printability is what any process technology development program starts with (not ends!), and these issues are one of the simplest to catch, and, more importantly, BK already disclosed that they moved to quintuple and sextuple patterning -- something not found in any of Intel's papers or presentations, afaik. So yes, it certainly looks like SAQP was identified as a problem very late in the process development, but any remaining printability issues must have been rectified by moving to 5x and 6x patterning.

As unbelievable as it would seem many years ago, current generation of Intel's process engineers (whether too old and uninterested or, vice versa, too inexperienced) appear simply unprepared to face the challenges posed by the process they're developing. OTOH, they are but victims of someone's decision to employ heterogeneous CuCo stack -- be it due to arrogance, lack of skill, or something else.

The point of "something else" here is it's not clear where exactly the idea of heteregoneous CuCo stack comes from. Was it born inside Intel? Not necessarily in my opinion. AMAT's history of cobalt-related developments goes back many years. Could it be that they thought using cobalt in several lower levels of metallization stack was a brilliant idea and started pitching it to fabs and chipmakers, finally succeeding with Intel? Before dismissing this as yet another conspiracy theory, keep in mind Intel has a history of buying into crap pitched to them that goes back many years as well (Itanium comes to mind), so in my opinion anything is possible.

Again, cobalt is 12x-13x more expensive than Cu, and I guess not only Co suppliers, but also AMAT would be very happy if Co is employed not only for liners, caps and contacts, but is adopted by the industry as a replacement for Cu for several levels of interconnect stack as they're advocating. Lots of $$$ in there -- and a lot at stake for some people at Intel now.

But given Intel's progress with 10nm process, current availability of analysis reports from Techinsights and GloFo's initial bet on CuCo stack, as follows from their 2016 IEDM 7nm paper, but apparent review of their initial plans to use it, I think there's simply no way industry is going to repeat Intel's mistake and employ heterogeneous CuCo stack. Not for the nearest nodes, and likely never in the future.

The jury is still out whether Samsung reviewed their plans to employ heterogeneous CuCo metal stack for 7nm process; given lack of coverage I take it they decided not to disclose it during their VLSI Symposium talk. I have a hunch that they reviewed their plans, but in case they didn't, I'm afraid they have the same troubles ahead as Intel.

There's no doubt for me there are enough bright engineers at Intel who understand all of this very well and simply wonder why they should bother at all and waste their lives teaching this pig to fly. Team morale suffers heavily in such situations -- it happend at Intel with Merced 20-25 years ago, and 10nm is Intel's process-technology Merced all over again.

Well, I think that's it for today, folks. Again, my big thanks to the forum member who kindly shared Intel's IITC paper with me.
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TopicPosted ByDate
Intel's 10nm IITC paper and AMAT's pubs provide some cluesAM2018/06/22 11:50 AM
  Noone to weigh in? C'mon, guys, it's RWT!AM2018/06/25 10:33 AM
    Noone to weigh in? C'mon, guys, it's RWT!Don'tknowenoughtoparticipate2018/07/03 09:13 AM
      Old newsAM2018/07/03 11:10 AM
  Intel's 10nm IITC paper and AMAT's pubs provide some cluesNoSpammer2018/06/28 05:56 AM
    Intel's 10nm IITC paper and AMAT's pubs provide some cluesjokerman2018/06/28 10:06 AM
      Intel's 10nm IITC paper and AMAT's pubs provide some cluesAM2018/06/28 12:53 PM
        Intel's 10nm IITC paper and AMAT's pubs provide some cluesMaxwell2018/06/29 05:53 PM
          Intel's 10nm IITC paper and AMAT's pubs provide some cluesAM2018/06/30 08:50 AM
        Intel's 10nm IITC paper and AMAT's pubs provide some cluesAlberto2018/07/01 08:46 AM
          Intel's 10nm IITC paper and AMAT's pubs provide some cluesDoug S2018/07/01 03:17 PM
            Intel's 10nm IITC paper and AMAT's pubs provide some cluesMaynard Handley2018/07/01 05:56 PM
              Intel's 10nm IITC paper and AMAT's pubs provide some cluesAlberto2018/07/02 01:40 AM
                Intel's 10nm IITC paper and AMAT's pubs provide some cluesBrett2018/07/02 10:45 AM
                Intel's 10nm IITC paper and AMAT's pubs provide some cluesDoug S2018/07/02 10:58 AM
            Only Samsung shows the realty. Alberto2018/07/02 01:13 AM
              Only Samsung shows the realty. Eric Bron2018/07/02 02:16 AM
                Only Samsung shows the realty. Alberto2018/07/02 02:35 AM
                  Only Samsung shows the realty. Doug S2018/07/02 10:53 AM
                    Only Samsung shows the realty. Michael S2018/07/02 11:12 AM
                      Only Samsung shows the realty. anon2018/07/02 02:27 PM
          Alberto, start with facts instead of posting nonsenseAM2018/07/03 11:19 AM
    What's this? Where from? (NT)AM2018/06/28 12:47 PM
    Intel's 10nm IITC paper and AMAT's pubs provide some cluesTapa Ghosh2018/06/30 11:37 AM
  Intel's 10nm IITC paper and AMAT's pubs provide some cluesIII-V2018/06/29 06:41 PM
    Intel's 10nm IITC paper and AMAT's pubs provide some cluesAM2018/06/30 08:44 AM
      Intel's 10nm IITC paper and AMAT's pubs provide some cluesTapa Ghosh2018/06/30 11:47 AM
  RE: Cobalt performanceIII-V2018/06/29 06:54 PM
    RE: Cobalt performanceAM2018/06/30 08:34 AM
      RE: Cobalt performanceIII-V2018/06/30 07:48 PM
        RE: Cobalt performanceEric Bron2018/07/01 01:07 AM
          RE: Cobalt performanceMichael S2018/07/01 03:27 AM
            RE: Cobalt performanceEric Bron2018/07/01 05:09 AM
              RE: Cobalt performanceEric Bron2018/07/01 05:10 AM
                Ice Lake in 10nm+Eric Bron2018/07/01 05:12 AM
              RE: Cobalt performanceDoug S2018/07/01 06:52 AM
                RE: Cobalt performanceanon2018/07/01 08:37 AM
                  RE: Cobalt performanceMichael S2018/07/01 08:41 AM
            RE: Cobalt performancejuanrga2018/07/01 05:33 AM
              RE: Cobalt performanceMichael S2018/07/01 05:59 AM
                François Piednoël (NT)juanrga2018/07/01 06:32 AM
                RE: Cobalt performanceEric Bron2018/07/01 06:42 AM
                  RE: Cobalt performanceEric Bron2018/07/01 06:44 AM
                    RE: Cobalt performanceMichael S2018/07/01 06:56 AM
                RE: Cobalt performanceAdrian2018/07/01 07:13 AM
                RE: Cobalt performanceMaynard Handley2018/07/01 10:54 AM
                  RE: Cobalt performanceMichael S2018/07/01 11:58 AM
          10 nm slidesEric Bron2018/07/01 10:20 AM
            10 nm slidesAlberto2018/07/02 02:23 AM
          RE: Cobalt performanceIII-V2018/07/01 09:11 PM
            RE: Cobalt performanceAdrian2018/07/02 03:16 AM
              RE: Cobalt performanceAlberto2018/07/02 04:10 AM
                RE: Cobalt performanceAdrian2018/07/02 07:34 AM
                Cobalt performance or fin height?Doug S2018/07/02 01:10 PM
                  Cobalt performance or fin height?AM2018/07/03 11:07 AM
            RE: Cobalt performanceEric Bron2018/07/02 08:21 AM
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