Former chicken farmer sentiments

By: Jeff S. (fakity.delete@this.fake.com), August 6, 2018 10:48 am
Room: Moderated Discussions
About a decade back, I had the opportunity to experiment with Tilera CPUs, which was the very embodiment of the "chicken flock" model. If there is not already some corollary to Amdahl's Law about reverse scaling when your shrunk cores bottleneck your serial paths far faster than the parallel parts get you any gain, there ought to be. The big+little model should go quite a way to alleviate these types of concerns, but it was just little+litle^little when I was doing any of this. The experience was formative, and my hat goes off to Tilera for making the platform perform as well as it did, but there were and are a lot of challenges in getting arbitrary problems to fit in a chicken-flock shaped mold, especially when done by a (then) junior developer.

A grab-bag of responses to random earlier comments:

wumpus (lost.delete@this.in.a.cave) on August 6, 2018 9:54 am wrote:
> Brett (ggtgp.delete@this.yahoo.com) on August 5, 2018 10:27 pm wrote:

> > One can use this information to predict what configuration the powerful but
> > cheap laptop Linus will be buying in 2 or 8 years or so will look like.
> > A PlayStation configuration of 4-8 real X86 cores surrounded by 16-32 helper cores.
> > The helper cores will be more than powerful enough to compile Linux.
> > When I say PlayStation I mean it, the very same chip as will be being
> > used in that generation of consoles, also available in the PC market.

Flock of chickens is hot garbage with RT and quasi-RT applications, which console video games will continue to be until variable refresh displays are universally deployed. Also, Sony learned their lesson with SPUs and will likely stay gun-shy about needlessly heterogeneous architectures for the near future. Yes, you can try to shrink working sets to fit chicken-local caches, but this is not much fun with some of the smaller chickens.

> > > > > I, in contrast, contend that SMT was and is a bad technology choice whose only justification
> > > > > is business/legal (eg IBM's bizarre contortions with POWER to create things that look for all
> > > > > the world like dual cores, but which can claim to be single cores for licensing purpose).

I think you're improperly conflating POWER's "super-slice" contortions with virtually every other SMT implementation do date that just tries to hide read latencies in applications that are not able to keep their working set anywhere close to 2x/4x etc. of their cache size and have relatively low register/execution unit pressure.

> > > > For server workloads the mm2 tradeoff of SMT clearly is a win.
> > > > This is why AMD added SMT even though SMT no longer makes sense on the desk/laptop.
> > > > At 2 cores and below one can make a weak case for SMT, not today with plentiful cores.

Agreed. AMD clearly needed Zen/Zeppelin to be a Jack-of-all-trades, but it absolutely needed enterprise as their long-term primary target in order to survive.

> Don't forget that AMD's memory fabric leaves with a dilemma: if the threads are using the same memory footprint,
> you beat yourself against AMD's memory fabric. If they are independent, you will need at least 4M (8mm) of
> L3 per flock just to *only* linearly increase the amount of bandwidth consumed by the memory interface: if
> you spammed more cores (and are hitting memory limits) you will need a lot more L3. Even with a better fabric
> (like a presumed Intel chip might have) will still need plenty of L3 to avoid memory bottlenecks.

Shared and especially distributed LLC is a double-edged sword. Flat and broad fabrics can look nice in the uncongested case, but snoop/fill traffic consumes precious bandwidth along every hop in the path between requesting, redirecting, and servicing nodes. Cluster on Die and Sub-NUMA Clustering are IMO just the beginning of walking back some of the ostensible promises of the architecture, just as CAT is a big band-aid to keep a burgeoning core population from devolving as quickly into degenerate free-for-alls or letting a few bad neighbors ruin everybody's hit rates. CCX-aware programming now is rightfully seen as a little bit of a PITA, but I think the general future has to look more like that than Skylake-X.

> As far as "spamming these flocks of feline chickens" we run into even worse issues: the zepplin die is
> 23% core, 17% L3, and 60% "everything else". It would be a miracle if "everything else" merely scaled
> linearly with cores (either floorspace or power consumption).

Even if CCX area is less than half a Zeppelin, it is hard to image the IO and chipset pieces needing to scale with core counts, and that is easily half of the remainder space:

annotated Zeppelin die shot from WikiChip

Sure the Infinity Fabric crossbar needs to scale something along the lines of quadratically with port count, but adding even a 3rd or 4th CCX would only raise the port count from 11 to 12 or 13.

> Also AMD really doesn't have a good interconnect
> fabric: spamming strong zepplin cores (Epyc and Threadripper) seems to work fine on most jobs, but I doubt
> you want to push it with weak kittens.

I think you need to substantiate your argument here better. Calling IF "less architecturally flat" than Skylake-X etc. would be more defensible, but there is no law that a chicken flock needs to utterly homogeneous either.

> The only thing that has changed since Seymour Cray uttered that bit about "flock of chickens vs. strong oxen"
> is that oxen have hit an upper limit in size. If you are going to spam cores (via sockets or on die), spam
> oxen. The issues on cache coherent networks, the scaling factors, and simple physics all conspire against
> spamming cores, and they hurt the less powerful ones a lot more.

Amen.

My forecast though is not that core counts won't rise, but that default, system-wide coherency eventually has to go the way of the 12 mpg 1960s Mustangs: it's something that doesn't scale indefinitely, and it will be viewed in hindsight as an extravagance that was a product of its ephemeral era. I see AMD's CCX approach of fabric hierarchies as moving gently in direction, since even though it allows broad coherency domains, you basically need to build software around the principle of try not to do so..
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TopicPosted ByDate
Ha ha ha ha haMaynard Handley2018/07/25 03:42 PM
  Ha ha ha ha haDB2018/07/25 03:55 PM
    Ha ha ha ha haMaynard Handley2018/07/25 04:07 PM
      Ha ha ha ha hawumpus2018/07/25 05:22 PM
        Ha ha ha ha hagallier22018/07/26 12:37 AM
          Ha ha ha ha haDavid Hess2018/07/26 02:41 PM
        Ha ha ha ha haDavid Hess2018/07/26 02:29 PM
          Ha ha ha ha hagallier22018/07/26 11:12 PM
            Ha ha ha ha harwessel2018/07/27 07:48 AM
              Ha ha ha ha hawumpus2018/07/27 08:46 AM
                Ha ha ha ha haDavid Hess2018/07/29 05:01 PM
                  Ha ha ha ha haAdrian2018/07/29 08:18 PM
                    Ha ha ha ha harwessel2018/07/29 11:48 PM
                  Ha ha ha ha hagallier22018/07/30 12:13 AM
                    Ha ha ha ha haMichael S2018/07/30 03:02 AM
      8C/8T > 6C/12TAndrew2018/07/25 05:57 PM
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      Ha ha ha ha haDB2018/07/25 08:43 PM
      Ha ha ha ha haDoug S2018/07/25 10:29 PM
      Ha ha ha ha haFoo_2018/07/26 02:01 AM
      Ha ha ha ha haDavid Hess2018/07/26 02:39 PM
        Ha ha ha ha haMaynard Handley2018/07/26 02:57 PM
          Ha ha ha ha haDavid Hess2018/07/26 03:20 PM
            Ha ha ha ha haAnon2018/07/27 12:33 AM
              Ha ha ha ha haDavid Hess2018/07/29 04:42 PM
          Ha ha ha ha haPassing Through2018/07/26 03:27 PM
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            Ha ha ha ha haTravis2018/07/26 08:25 PM
              Ha ha ha ha haPassing Through2018/07/27 03:52 AM
          Ha ha ha ha haJukka Larja2018/07/27 09:17 AM
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      Ha ha ha ha haJukka Larja2018/07/26 06:05 AM
        Ha ha ha ha haEmil Briggs2018/07/26 07:06 AM
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                              revelationBrett2018/08/08 08:05 PM
                                revelationGabriele Svelto2018/08/09 03:15 PM
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                            Really weak cakculations , exrapolating after extrapolation juanrga2018/08/10 01:47 AM
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                            Marketed prize vs manufacturing cost of SMTBrett2018/08/09 08:25 PM
            Multi-core versus singlePassing Through2018/07/26 12:29 PM
            Multi-core versus singleanon2018/07/26 07:23 PM
            Multi-core versus singleDoug S2018/07/26 10:41 PM
              SMT already present on smartphonesmpx2018/07/27 02:26 AM
                SMT or FgMT? (NT)Heikki Kultala2018/07/27 08:28 PM
            Multi-core versus singlewumpus2018/07/27 06:05 AM
    Ha ha ha ha haanon.12018/07/26 08:56 AM
      Ha ha ha ha haPassing Through2018/07/26 09:24 AM
        Capture and encoding - real world examplePassing Through2018/07/26 09:30 AM
        Ha ha ha ha haAaron Spink2018/07/26 04:48 PM
          Ha ha ha ha haPassing Through2018/07/27 04:11 AM
          A Top Tier Streamer ? Passing Through2018/07/27 04:42 AM
            A Top Tier Streamer ? Passing Through2018/07/27 05:16 AM
              A Top Tier Streamer ? Passing Through2018/07/27 09:59 AM
                A Top Tier Streamer ? Kevin G2018/07/29 01:03 PM
      Ha ha ha ha haMaynard Handley2018/07/26 06:00 PM
        Ha ha ha ha haJukka Larja2018/07/27 08:59 AM
        Ha ha ha ha haanon.12018/07/27 07:24 PM
  i9-9900k, i7-9700k, and i5-9600k specificationsjuanrga2018/07/26 02:06 AM
    9900k/9700k L3 difference too?Jeff S.2018/07/26 05:07 AM
      9900k/9700k L3 difference too?Anon2018/07/26 05:16 AM
      9900k/9700k L3 difference too?Jukka Larja2018/07/26 06:10 AM
        silicon harvesting?hobold2018/07/26 06:40 AM
  Top chip still has hyperthreadingSeriously2018/07/28 07:22 AM
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