TIL: simple vs complex addressing is resolved at rename time (probably)

By: foobar (foobar.delete@this.foobar.foobar), August 4, 2018 1:40 am
Room: Moderated Discussions
Travis (travis.downs.delete@this.gmail.com) on August 3, 2018 1:34 pm wrote:
> What I learned yesterday that the distinction between simple and complex addressing apparently
> happens dynamically after decode. In particular, something like [rdx + rsi*4] looks like
> complex addressing, but if rsi is zero at runtime and was set to zero by a zeroing idiom
> the latency is as-if you were using simple addressing (4 cycles for GP loads).

This made me wonder: would the same be possible for conditional branches? That is, if you would use the zero idiom on a register and perform a macro-fused compare-and-branch operation not involving other registers on it, the executed uop would actually be an unconditional jump, or even a nop if the conditional branch would not be taken? I guess this would be visible mostly through the branch predictor since predicted taken branches have the same performance as unconditional jumps...
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TopicPosted ByDate
TIL: simple vs complex addressing is resolved at rename time (probably)Travis2018/08/03 01:34 PM
  TIL: simple vs complex addressing is resolved at rename time (probably)foobar2018/08/04 01:40 AM
    TIL: simple vs complex addressing is resolved at rename time (probably)anon2018/08/04 05:05 AM
      TIL: simple vs complex addressing is resolved at rename time (probably)foobar2018/08/04 07:00 AM
        TIL: simple vs complex addressing is resolved at rename time (probably)anon2018/08/04 08:32 AM
          TIL: simple vs complex addressing is resolved at rename time (probably)foobar2018/08/04 09:48 AM
            TIL: simple vs complex addressing is resolved at rename time (probably)anon2018/08/04 10:19 AM
  Data-dependent instruction latencyPeter E. Fry2018/08/04 07:14 AM
    ... or a compiler optimizing aggressively?Heikki Kultala2018/08/04 08:13 AM
      ... or a compiler optimizing aggressively?Peter E. Fry2018/08/04 08:53 AM
    Data-dependent instruction latencyTravis2018/08/04 03:33 PM
      Data-dependent instruction latencyPeter E. Fry2018/08/05 09:13 AM
        Data-dependent instruction latencyTravis2018/08/05 04:55 PM
          Data-dependent instruction latencyPeter E. Fry2018/08/06 07:34 AM
            Data-dependent instruction latencyTravis2018/08/06 05:10 PM
              Data-dependent instruction latencyPeter E. Fry2018/08/07 07:09 AM
                Data-dependent instruction latencyPeter E. Fry2018/08/07 07:11 AM
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