matthew (nobody.delete@this.example.com) on August 19, 2018 2:48 pm wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on August 19, 2018 2:36 pm wrote:
> > matthew (nobody.delete@this.example.com) on August 19, 2018 2:32 pm wrote:
> > > Michael S (already5chosen.delete@this.yahoo.com) on August 19, 2018 1:58 pm wrote:
> > > > matthew (nobody.delete@this.example.com) on August 19, 2018 12:51 pm wrote:
> > > > > I think there's a good counter-example to your point, which is the Itanium McKinley implementation
> > > > > of fetchadd. If the line is in L1, the CPU does it. If it's not, the core tells the
> > > > > L2 to do it.
> > > >
> > > > Are you sure?
> > > > Do you have a proof link?
> > >
> > > I was working at HP at the time (on the Linux team), and it was common knowledge. I see
> > > the wikipedia page on IA-64 has the same information, "The 256 KB L2 cache contains sufficient
> > > logic to handle semaphore operations without disturbing the main arithmetic logic unit (ALU)."
> > > but it doesn't cite a source. I can't find anything authoritative right now.
> > >
> >
> > My copies of I2 manuals certainly do not contain anything of that sort.
> >
>
> Found a paper from ISSCC 2002:
>
> "The L2 cache performs all semaphore operations on the proces-
> sor. The most involved of these RMW operations, fetch-add, is
> performed by circuitry capable of performing 64b bi-endian addi-
> tion without the need for an explicit rotation of data all within a
> 1-cycle budget. "
>
> https://zapdf.com/the-high-bandwidth-256-kb-2nd-level-cache-on-an-itanium-micr.html
>

Thank you.
I can't see how making common case 4-8 clocks slower than necessary is a good idea, but what I know?
However, as said by Travis, from the system perspective an operation is still strictly local, because from system perspective L2, L1s and core are parts of the same entity.