Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on August 22, 2018 3:07 pm wrote:
> anon (anon.delete@this.anon.com) on August 21, 2018 4:27 pm wrote:
> > I assume you mean each core sending a non-cache-coherent message off core somewhere (a memory
> > controller?) which atomically increments a single location. That's crazy. First of all you have
> > the same scaling problem, now you just offloaded it to the non-coherent messaging system and
> > the entity performing the remote atomic. Secondly, high performance use cases that would care
> > (like networking) literally count cache misses (or any type of operation that goes out of the
> > core). Adding one more per packet might cut your performance by double digit percentages.
>
> And yet there have been high-performance network processors implementing those.

Not a very convincing argument. There has been a lot of crap implemented. Transactional memory is a vast, massive complexity to hardware and everyone was warned before they started it that there are better ways to do scalable software, and yet high performance processors still implemented it.

I have no doubt that for a particular case study you can make something go faster if you take your old software and convert it to use remote atomics in some parts. Possibly even some niches like dedicated network processors where the feature does actually make sense.

I was mostly talking about high performance general purpose CPUs, but even in the case of network processor, depending on your exact requirements of the stats, I would not be surprised if stats counting could be kept local most of the time and save more energy and cost than shooting atomics to shared memory/cache all the time.