By: Jeff S. (fakity.delete@this.fake.com), August 24, 2018 12:39 pm
Room: Moderated Discussions
Maynard Handley (name99.delete@this.name99.org) on August 24, 2018 1:26 pm wrote:
> Jeff S. (fakity.delete@this.fake.com) on August 24, 2018 12:24 pm wrote:
> > This is the kind of thing I suspect David would very succinctly summarize as "dI/dt
> > concerns", but I don't have any real data or secret sources for you unfortunately.
> It seems that, in PRINCIPLE, you should be able to monitor the charge of a capacitor over time,
> and dynamically engage in clock-by-clock throttling (through things like halting fetch, decode,
> or issue); and that this would be more performant than just clubbing the frequency?
> Of course it takes time to design a scheme like that, but this has been an issue for years...
> It will be interesting to see if Apple has anything along those lines in the A12. Obviously
> the details are different, but they are clearly aware that they have their own problem
> with SoC power draw possibly exceeding what an (aged) battery can supply.
> One solution to that is the Intel solution, just reducing frequency (and only improved
> over the A11 and earlier solution in that there might be more intermediate frequency steps
> available, and/or a more dynamic monitor of when current draw is going high).
> But a more performant solution would be a variant of what I've described for AVX, something that perhaps
> monitors the big capacitor rather than the battery current, and throttles on a cycle by cycle basis.
I think you'd get screwed by Tomasulo (imagine a malicious instruction sequence of 100+ chained dependent FMAs waiting on a single load or something) unless you were willing to put the power checks into the tightest of tight timing regions of your core, but a more in-order chip could probably throttle things in the front end in a sane matter.
> Jeff S. (fakity.delete@this.fake.com) on August 24, 2018 12:24 pm wrote:
> > This is the kind of thing I suspect David would very succinctly summarize as "dI/dt
> > concerns", but I don't have any real data or secret sources for you unfortunately.
> It seems that, in PRINCIPLE, you should be able to monitor the charge of a capacitor over time,
> and dynamically engage in clock-by-clock throttling (through things like halting fetch, decode,
> or issue); and that this would be more performant than just clubbing the frequency?
> Of course it takes time to design a scheme like that, but this has been an issue for years...
> It will be interesting to see if Apple has anything along those lines in the A12. Obviously
> the details are different, but they are clearly aware that they have their own problem
> with SoC power draw possibly exceeding what an (aged) battery can supply.
> One solution to that is the Intel solution, just reducing frequency (and only improved
> over the A11 and earlier solution in that there might be more intermediate frequency steps
> available, and/or a more dynamic monitor of when current draw is going high).
> But a more performant solution would be a variant of what I've described for AVX, something that perhaps
> monitors the big capacitor rather than the battery current, and throttles on a cycle by cycle basis.
I think you'd get screwed by Tomasulo (imagine a malicious instruction sequence of 100+ chained dependent FMAs waiting on a single load or something) unless you were willing to put the power checks into the tightest of tight timing regions of your core, but a more in-order chip could probably throttle things in the front end in a sane matter.
