By: David Hess (davidwhess.delete@this.gmail.com), August 26, 2018 9:20 am
Room: Moderated Discussions
Brett (ggtgp.delete@this.yahoo.com) on August 25, 2018 1:58 pm wrote:
>
> There is also no law that the float/vector unit has to run at the same clock rate as the rest of the CPU.
> You just have to buffer the cache interface and the incoming decoded float/vector instruction
> stream, and buffer the incoming instruction completion signals for write commits.
>
> This would completely hide single slow vector instructions, you could detect this
> by having say every 20th instruction a vector op, the CPU should stay at 4+GHz.
I thought they might operate it synchronously at a small integer fraction of the clock speed like 2/3 or 4/5 instead of changing the clock speed of the entire core.
>
> There is also no law that the float/vector unit has to run at the same clock rate as the rest of the CPU.
> You just have to buffer the cache interface and the incoming decoded float/vector instruction
> stream, and buffer the incoming instruction completion signals for write commits.
>
> This would completely hide single slow vector instructions, you could detect this
> by having say every 20th instruction a vector op, the CPU should stay at 4+GHz.
I thought they might operate it synchronously at a small integer fraction of the clock speed like 2/3 or 4/5 instead of changing the clock speed of the entire core.
