AVX-512 possibly in its own clock domain?

By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), August 27, 2018 12:46 pm
Room: Moderated Discussions
Maynard Handley (name99.delete@this.name99.org) on August 26, 2018 5:35 pm wrote:
> And that certainly has happened in the past!
> Some of the PPCs (around say the PPC 750) had some sort of weird stutter, I can't remember the details, that
> meant that every sixth or fifth FP instruction was delayed by one cycle. This was "architected" in the sense
> that it was meant to happen, every n'th instruction (or perhaps every n'th clock) was devoted to what ever it
> was that took some cleanup, it wasn't an artifact of a particular sequence of FP instructions or data.
>
> With a brief search the best I can find is this which references the issue:
> https://cr.yp.to/hardware/ppc.html
> At the time I did know the details, but it's possible I learned them
> from reading internal Apple docs and they were never public? Oh well.

This was common (and documented!) behavior in all Motorola cores starting with the 603e and including the 7450. In the 603e manual it's described in paragraph 6.3.2.2 in the pipeline example:

In cycle 4, target instructions 8 and 9 are fetched. Instruction 1 completes in cycle 4, allowing instruction 2, which had finished executing in the previous clock cycle, to be removed from the CQ. Instruction 6 replaces instruction 3 in the first stage of the FPU. Also, as will be shown in cycle 5, a single-cycle stall occurs when the FPU pipeline is full.

You will find the exact same description in the 750 and 7400/7410 manuals. The 7450 is slightly different but only because the FPU pipeline was longer:

The five-stage scalar FPU pipeline has a 5-cycle latency. However, when the pipeline contains instructions in stages E0–E3, the pipeline stalls and does not allow a new instruction to start in E0 on the following cycle. This bubble limits maximum FPU throughput to four instructions every 5 cycles [...]

The 7450 had other weird limitations to scalar FP, stores were non-pipelined for example so that you could only do one every three cycles.
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