You can do two 4-cycle loads per cycle

By: anon (spam.delete.delete@this.this.spam.com), September 19, 2018 2:45 am
Room: Moderated Discussions
Wilco (Wilco.dijkstra.delete@this.ntlworld.com) on September 18, 2018 2:37 pm wrote:
> anon (spam.delete.delete@this.this.spam.com) on September 18, 2018 1:27 pm wrote:
> > Travis Downs (travis.downs.delete@this.gmail.com) on September 18, 2018 12:29 pm wrote:
> > > anon (spam.delete.delete@this.this.spam.com) on September 18, 2018 11:53 am wrote:
> > > > Travis Downs (travis.downs.delete@this.gmail.com) on September 18, 2018 10:58 am wrote:
> > > > > anon (spam.delete.delete@this.this.spam.com) on September 18, 2018 2:43 am wrote:
> > > > >
> > > > > > Can it do 2 fast path loads in the same cycle? If not it would make sense to prioritize pointer chases.
> > > > >
> > > > > Yes, it can - at least on SKL and IVB (the two archs I tested on).
> > > > ...
> > > > If throughput isn't the problem and it only happens when the loads immediately follow each
> > > > other then it might be something different. Maybe it's skipping the TLB lookup altogether.
> > >
> > > I think it still needs the TLB lookup, and in fact the TLB lookup is still more or less on
> > > the critical path since the addresses here are arbitrary and it needs the tag to select the
> > > right way from the L1D set, whose access happens in parallel. I don't think any type of way
> > > prediction is happening here since anyways the pointer chasing case doesn't lend itself to
> > > it and also the 4-cycle latency is consistent even with "randomly" distributed addresses.
> > >
> >
> > Then how do you explain the restriction? What prevents the use of the
> > fast path with registers that weren't the result of an earlier load?
>
> Hardware doesn't move between pipelines. If we assume 4-cycle loads skip the initial complex address
> calculation stage (and not a later stage), a 4-cycle load after a 5-cycle load must wait for a cycle
> simply because the pipeline stages it needs are still being used by the earlier load.
>
> Wilco
>

Am I missing something obvious here?
4 cycle loads exist.
What is the restriction that prevents them when the adress is the result of an ALU op instead of a load?
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TopicPosted ByDate
4-cycle L1 latency on Intel not as general as thoughTravis Downs2018/09/17 04:32 PM
  4-cycle L1 latency on Intel not as general as thoughanon2018/09/18 02:43 AM
    4-cycle L1 latency on Intel not as general as thoughtTravis Downs2018/09/18 09:39 AM
      4-cycle L1 latency on Intel not as general as thoughtanon2018/09/18 10:53 AM
        4-cycle L1 latency on Intel not as general as thoughtTravis Downs2018/09/18 11:07 AM
          4-cycle L1 latency on Intel not as general as thoughtanon2018/09/18 11:51 AM
            4-cycle L1 latency on Intel not as general as thoughtTravis Downs2018/09/18 01:52 PM
              4-cycle L1 latency on Intel not as general as thoughtanon2018/09/19 02:40 AM
                4-cycle L1 latency on Intel not as general as thoughtTravis Downs2018/09/19 05:20 PM
                  4-cycle L1 latency on Intel not as general as thoughtSeni2018/09/19 10:28 PM
                    4-cycle L1 latency on Intel not as general as thoughtGabriele Svelto2018/09/20 05:16 AM
                      4-cycle L1 latency on Intel not as general as thoughtTravis Downs2018/09/20 02:25 PM
                        4-cycle L1 latency on Intel not as general as thoughtGabriele Svelto2018/09/21 02:46 AM
                  4-cycle L1 latency on Intel not as general as thoughtanon2018/09/20 08:40 AM
                    4-cycle L1 latency on Intel not as general as thoughtTravis Downs2018/09/20 03:01 PM
    You can do two 4-cycle loads per cycleTravis Downs2018/09/18 10:58 AM
      You can do two 4-cycle loads per cycleanon2018/09/18 11:53 AM
        You can do two 4-cycle loads per cycleTravis Downs2018/09/18 12:29 PM
          You can do two 4-cycle loads per cycleanon2018/09/18 01:27 PM
            You can do two 4-cycle loads per cycleWilco2018/09/18 02:37 PM
              You can do two 4-cycle loads per cycleanon2018/09/19 02:45 AM
                You can do two 4-cycle loads per cycleTravis Downs2018/09/19 05:30 PM
                  You can do two 4-cycle loads per cycleanon2018/09/20 01:34 AM
                    You can do two 4-cycle loads per cycleWilco2018/09/20 02:32 AM
                      You can do two 4-cycle loads per cycleanon2018/09/20 04:35 AM
                      You can do two 4-cycle loads per cycleTravis Downs2018/09/20 03:33 PM
                    You can do two 4-cycle loads per cycleTravis Downs2018/09/20 03:10 PM
            You can do two 4-cycle loads per cycleTravis Downs2018/09/18 03:08 PM
              You can do two 4-cycle loads per cycleGabriele Svelto2018/09/19 01:39 AM
                You can do two 4-cycle loads per cycleTravis Downs2018/09/19 05:43 PM
              You can do two 4-cycle loads per cycleanon2018/09/19 02:42 AM
                You can do two 4-cycle loads per cycleTravis Downs2018/09/19 06:09 PM
                  You can do two 4-cycle loads per cycleanon2018/09/20 01:49 AM
                    You can do two 4-cycle loads per cycleTravis Downs2018/09/20 04:38 PM
                    You can do two 4-cycle loads per cycleTravis Downs2018/09/20 07:27 PM
                      You can do two 4-cycle loads per cycleanon2018/09/21 08:08 AM
            Separate RS for ALU vs load/storeTravis Downs2018/12/13 12:55 PM
              Separate RS for ALU vs load/storeanon2018/12/13 02:14 PM
              Separate RS for ALU vs load/storeanon.12018/12/13 09:15 PM
                Separate RS for ALU vs load/storeWilco2018/12/14 04:41 AM
                  Separate RS for ALU vs load/storeanon.12018/12/14 08:08 AM
                    Separate RS for ALU vs load/storeWilco2018/12/14 01:51 PM
              Integer divide also var latencyDavid Kanter2018/12/14 11:45 AM
                Integer divide also var latencyTravis Downs2018/12/14 09:09 PM
              Separate RS for ALU vs load/storeanon22018/12/14 09:57 PM
                Separate RS for ALU vs load/storeTravis Downs2018/12/15 11:00 AM
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