By: Travis Downs (travis.downs.delete@this.gmail.com), September 19, 2018 5:43 pm
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on September 19, 2018 1:39 am wrote:
> Having variable latencies also makes your scheduler more complex so it must be worth it.
I had though that latency is known early enough that this just looks like another fixed latency instruction. In particular, I thought that by the time it gets into the scheduler, the uop probably already knows whether it's 4-cycle, 5-cycle, etc. In particular because it seems that the 4 vs 5 cycle decision might have been made in the RAT since indexed addressing but where the index register is zeroed with a zeroing idiom still uses the 4-cycle path.
This recent stuff leaves me not so sure. It seems like the "comes from an ALU op" thing could be resolved by the renamer too, but the "last load was replayed" seems less likely, unless there is some feedback from later in the pipeline that enables that. Maybe the scheduler keeps track of that: when a replay happens it knows its going to execute the next 4-cycle load as 5-cycle.
> Having variable latencies also makes your scheduler more complex so it must be worth it.
I had though that latency is known early enough that this just looks like another fixed latency instruction. In particular, I thought that by the time it gets into the scheduler, the uop probably already knows whether it's 4-cycle, 5-cycle, etc. In particular because it seems that the 4 vs 5 cycle decision might have been made in the RAT since indexed addressing but where the index register is zeroed with a zeroing idiom still uses the 4-cycle path.
This recent stuff leaves me not so sure. It seems like the "comes from an ALU op" thing could be resolved by the renamer too, but the "last load was replayed" seems less likely, unless there is some feedback from later in the pipeline that enables that. Maybe the scheduler keeps track of that: when a replay happens it knows its going to execute the next 4-cycle load as 5-cycle.
