By: Travis Downs (travis.downs.delete@this.gmail.com), December 13, 2018 12:55 pm
Room: Moderated Discussions
anon (spam.delete.delete@this.this.spam.com) on September 18, 2018 12:27 pm wrote:
> Then how do you explain the restriction? What prevents the use of the
> fast path with registers that weren't the result of an earlier load?
Something that might be related to the 1-cycle longer latency for pointer chasing loops that have an ALU op came up in the Sunny Cove slides:
In the "Skylake reminder" it clearly shows that there is a separate RS for the 3 AGUs. That's the first I've hard of this possibility (Intel usually describes their scheduler as a single unified scheduler, so it comes as a bit of a surprise).
Perhaps a separate scheduler is used because the implementation for loads is more complicated due to replay considerations (although really it complicates all the dependent operations) or because these are the only (?) uops with variable latency. In any case, it could imply that the extra cycle occurs because of cross-RS delays: such as the AGU is the only one that knows whether an op is 4 or 5 latency, so operations in the ALU RS just wake up with conservative value of 5 cycles, which almost always works.
Or, the slide could just be wrong. There are other errors there, like where it shows the scalar mul unit on p5 in SKL, but it is actually on p1 there (and so Anandtech subsequently mentioned that the mul unit is moving around based on this incorrect slide). Still it looks deliberate to me how they have broken up the RS boxes, not just a quirk of the diagram.
Or, the slide could be right but the separate RS has no practical impact on the load->ALU latency.
> Then how do you explain the restriction? What prevents the use of the
> fast path with registers that weren't the result of an earlier load?
Something that might be related to the 1-cycle longer latency for pointer chasing loops that have an ALU op came up in the Sunny Cove slides:
In the "Skylake reminder" it clearly shows that there is a separate RS for the 3 AGUs. That's the first I've hard of this possibility (Intel usually describes their scheduler as a single unified scheduler, so it comes as a bit of a surprise).
Perhaps a separate scheduler is used because the implementation for loads is more complicated due to replay considerations (although really it complicates all the dependent operations) or because these are the only (?) uops with variable latency. In any case, it could imply that the extra cycle occurs because of cross-RS delays: such as the AGU is the only one that knows whether an op is 4 or 5 latency, so operations in the ALU RS just wake up with conservative value of 5 cycles, which almost always works.
Or, the slide could just be wrong. There are other errors there, like where it shows the scalar mul unit on p5 in SKL, but it is actually on p1 there (and so Anandtech subsequently mentioned that the mul unit is moving around based on this incorrect slide). Still it looks deliberate to me how they have broken up the RS boxes, not just a quirk of the diagram.
Or, the slide could be right but the separate RS has no practical impact on the load->ALU latency.
