MultiChip Rumors

By: Maynard Handley (name99.delete@this.name99.org), September 21, 2018 2:06 pm
Room: Moderated Discussions
dmcq (dmcq.delete@this.fano.co.uk) on September 21, 2018 12:22 pm wrote:
> dmcq (dmcq.delete@this.fano.co.uk) on September 21, 2018 12:18 pm wrote:
> > wumpus (lost.delete@this.in.a.cave) on September 21, 2018 8:14 am wrote:
> > > dmcq (dmcq.delete@this.fano.co.uk) on September 21, 2018 5:28 am wrote:
> > > [deleted]
> > >
> > > >
> > > > If you look you'll notice I talked about having a third party doingthe integrating like for a PCB nowadays.
> > > >
> > >
> > > I can't see Intel handing out the keys to EMIB to third parties,
> > > nor can I see anyone at Intel letting the EMIB
> > > guys near the process except to blame them for delays. I'd
> > > expect them to be at an impasse. Unless a competing
> > > means of creating MCM takes over, I'd expect EMIB to still push forward after Intel gets 10nm going.
> > >
> > > AMD has used traditional (as far as I know) techniques on
> > > EPYC and an interposer for Vega. EPYC worked great
> > > (if expensive, but EPYC has margins) and Vega isn't going
> > > anywhere. I'd be fairly shocked if Rome didn't follow
> > > Zepplin's lead. Although they are splitting between server
> > > and consumer this time, I'd still expect Rome to
> > > handle both "small servers" and "largeish servers" in a single socket, which probably means a MCM.
> > >
> > > There's also the issue of AMD's intercore fabric. It might not have any advantages
> > > with any interconnect faster than the current MCM, although I'd expect this is
> > > something AMD went straight to work on once more money came rolling in.
> > >
> > > >
> > > > Good luck with putting memory and CPU on the same chip.
> > > > [deleted]
> > > [wild layman speculation follows, ignore except for humorous value:)]
> > > If the processes for logic and DRAM are incompatible, I'd assume that any attempt to do so requires
> > > building an entire wafer's worth (i.e. covering the whole chip) with either logic or storage. There
> > > have certainly been enough "2 layer chips" done as research projects, although I'm not sure if this
> > > was done one both sides or with a sufficiently wide barrier and a second chip on top (just make sure
> > > the bottom layer doesn't require significant cooling. This might limit you to something like NVMe
> > > things that don't require constant power (the latency might be unacceptable for most CPUs, perhaps
> > > a threaded GPU-style processor can eat the latency in return for unlimited bandwidth)
> > >
> > > PCBs have used both sides of the epoxy for a long time, why not chips? It all comes down
> > > to logic and high density storage having incompatible processes, and how to get the twain
> > > to meet (I'd still bet on EMIB even if they can't get near any chip smaller than 22nm).
> >
> > Thru hole vias are a problem, not having them in the high
> > density interconnect bridges in EMIB is a big advantage
>
> Or a through silicon vias as they are called for silicon interposers

I've no idea what you're saying here.
Let's clarify two points.
(a) What, in your opinion, is special about EMIB compared to any other 2.5D technology? Yes, the Si slivers are smaller, and the traces are more dense. But those are simply more aggressive implementations of known ideas.
I'm willing to concede that there is KNOW-HOW in EMIB that's not been (yet) established at other companies. What I don't see is anything special there that's fundamentally new and beyond standard development know-how. ie Intel got there first purely because they wanted to get their first (because they charge the highest prices and this was a high price technique).

(b) You seem to be asserting that 2.5D (ie EMIB and related technologies) are generically superior to 3D technologies. This is an unorthodox take, and what justifies it?

Once again I remind everyone that there's a great overview of this stuff here:
https://community.arm.com/arm-research/b/articles/posts/three-dimensions-in-3dic-part-1
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
MultiChip Rumorstm.at.VR2018/09/21 12:32 AM
  MultiChip Rumorsdmcq2018/09/21 02:33 AM
    MultiChip RumorsMichael S2018/09/21 03:30 AM
      MultiChip Rumorsdmcq2018/09/21 03:58 AM
        MultiChip RumorsMichael S2018/09/21 04:47 AM
          MultiChip Rumorsdmcq2018/09/21 05:28 AM
            putting memory and CPU on the same chipEtienne2018/09/21 06:32 AM
              putting memory and CPU on the same chipMichael S2018/09/21 07:20 AM
              putting memory and CPU on the same chipanon2018/09/21 09:09 AM
            MultiChip Rumorswumpus2018/09/21 08:14 AM
              MultiChip Rumorsdmcq2018/09/21 12:18 PM
                MultiChip Rumorsdmcq2018/09/21 12:22 PM
                  MultiChip RumorsMaynard Handley2018/09/21 02:06 PM
                    MultiChip RumorsDavid Kanter2018/09/21 04:52 PM
                      MultiChip RumorsMaynard Handley2018/09/21 05:04 PM
                        Already in mainstreamjohn2018/09/21 11:04 PM
                          Already in mainstream ???wumpus2018/09/22 07:37 AM
                            Already in mainstream ???Adrian2018/09/22 08:12 AM
                              Already in mainstream ???wumpus2018/09/22 01:24 PM
                                Kaby Lake G EMIB.Heikki Kultala2018/09/23 05:32 AM
                            Already in mainstream ???blue2018/09/22 08:29 AM
                          Already in mainstreamjuanrga2018/09/22 11:13 AM
                    MultiChip Rumorsdmcq2018/09/22 04:53 AM
                    MultiChip Rumorsjuanrga2018/09/22 11:07 AM
                      MultiChip RumorsMaynard Handley2018/09/22 11:31 AM
                        MultiChip Rumorscarop2018/09/22 01:34 PM
              MultiChip RumorsMaynard Handley2018/09/21 01:57 PM
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