epyc 2

By: dimagio (ntinos75.delete@this.gmail.com), September 25, 2018 11:34 pm
Room: Moderated Discussions
epyc 2 with L4 edram cache?
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epyc 2dimagio2018/09/25 11:34 PM
  epyc 2determinator2018/09/26 12:02 AM
  No. TSMC "7nm" does not support it. (NT)Heikki Kultala2018/09/26 11:17 AM
    Might have eDRAM after all.Heikki Kultala2018/11/07 04:30 AM
      Might have eDRAM after all.juanrga2018/11/08 01:55 AM
        Might have eDRAM after all.Doug S2018/11/08 10:07 AM
  epyc 2y a anon2018/09/26 01:35 PM
    epyc 2Michael S2018/09/27 03:01 AM
      epyc 2: eDRAM vs. DRAM [warning, rambles long afterwards about caches for post-DRAM memory]wumpus2018/09/27 08:10 AM
        epyc 2: eDRAM vs. DRAM [warning, rambles long afterwards about caches for post-DRAM memory]Jukka Larja2018/09/28 10:55 PM
          epyc 2: eDRAM vs. DRAM [warning, rambles long afterwards about caches for post-DRAM memory]Jeff S.2018/09/29 03:44 AM
            epyc 2: eDRAM vs. DRAM [warning, rambles long afterwards about caches for post-DRAM memory]Jukka Larja2018/09/30 12:16 AM
              epyc 2: eDRAM vs. DRAM [warning, rambles long afterwards about caches for post-DRAM memory]Jeff S.2018/09/30 06:33 AM
                epyc 2: eDRAM vs. DRAM [warning, rambles long afterwards about caches for post-DRAM memory]Jukka Larja2018/10/01 04:47 AM
                  epyc 2: eDRAM vs. DRAM [warning, rambles long afterwards about caches for post-DRAM memory]anon2018/10/01 05:53 AM
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