Kevin G (kevin.delete@this.cubitdesigns.com) on October 4, 2018 1:47 pm wrote:
> The line about embedding some of these chips into the layers of the motherboard seems a bit improbable.
> It would only make sense if the existing manufacturing lines supported this but my impression of the
> market is that such manufacturing is only used in mobile applications where space is at a very high
> premium. Various network and server hardware doesn't use that level of board level integration to my
> knowledge (though I will admit if it is used, slipping in a chip between PCB layers is indeed a very
> clever means of hiding a chip).

This reminded me of this post from the Talos workstation crowfunding drive:

Talos FPGA Functions and Responsibilities - Part 1

What is LPC Guard™?

In a nutshell, LPC Guard™ converts the traditional monolithic shared LPC bus topology into a pseudo-star topology, then masks sensitive data transmissions involving a single peripheral from all remaining peripherals on the bus. The bus control device central to this technology is securely connected to the LPC master onboard the CPU or southbridge device, with the associated PCB traces located in central layers of the system board. All LPC peripherals attach directly to this bus control device, thus allowing the bus controller to modify all data and control signals being sent to and from the LPC master and each peripheral. From the perspective of the LPC master and peripherals, the normal shared LPC bus is logically present, although it is not physically present. This modification does not alter LPC compatibility in any way. For additional security, sensitive peripherals also securely connect to the bus controller, with the associated PCB traces located in central layers of the system board.

Emphasis mine. Since they're still developing this kind of hardware I'm pretty sure this news will help them secure another round of funding.