Why no EMIB?

By: anon.1 (abc.delete@this.def.com), November 7, 2018 8:00 am
Room: Moderated Discussions
Kevin G (kevin.delete@this.cubitdesigns.com) on November 6, 2018 8:06 am wrote:
> anon.1 (abc.delete@this.def.com) on November 6, 2018 7:15 am wrote:
> > anon (anon.delete@this.mailinator.com) on November 6, 2018 3:31 am wrote:
> > > dmcq (dmcq.delete@this.fano.co.uk) on November 6, 2018 2:45 am wrote:
> > > > Anandtech outlined a new Intel multi-chip packkage
> > > > Intel Goes For 48-Cores: Cascade-AP with Multi-Chip Package Coming Soon
> > > > but says they're not using EMIB, do you think perhaps Anandtech are wrong or why would
> > > > they not use EMIB? It seems made for the job and a unique advantage for Intel.
> > >
> > > EMIB requires the chips it's used with to be designed for it. This 48-core CPU just
> > > appears to be two existing Cascade Lake SP chips shipped in a single package, communicating
> > > through the same links they would be in a multi-socket system.
> > >
> > > If Intel designs a new chip specifically for use in such a system, they would probably use EMIB.
> > >
> > >
> >
> > Is it possible to put 2x 200W dies maybe a mm apart and not run into mechanical stresses
> > or thermal issues? So far, we've seen EMIB as a product used only on AMD Vega part on Intel
> > MCM. They chose not to put the CPUGPU interface on EMIB. Maybe there were legit management
> > reasons (schedule, time to market, complexity, working with another company etc), but that
> > would've been a great test vehicle for the idea and they didn't go all the way.
>
> EMIB is used on some FPGA parts like the Stratix 10 which have up to six EMIB tiles.
>
> Leveraging EMIB for a PCIe 8x link between the Vega GPU and Kaby Lake die would
> not have been a wise decision as it would not have brought performance increase
> or significant power consumption decreases. It would still have been an 8x link.

Ah, you're right, I forgot about Stratix. Re. EMIB/interposer, I thought the whole point of the thing was you go wider but slower. Data transfer rate stays the same but power goes down. That was AMD argument in a hotchips presentation in favor of HBM instead of GDDR. Does the same logic not apply? Thanks!
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Why no EMIB?dmcq2018/11/06 03:45 AM
  Why no EMIB?anon2018/11/06 04:31 AM
    Why no EMIB?anon.12018/11/06 08:15 AM
      Why no EMIB?Kevin G2018/11/06 09:06 AM
        Why no EMIB?useruser2018/11/06 10:41 AM
        Why no EMIB?anon.12018/11/07 08:00 AM
          Why no EMIB?Jeff S.2018/11/07 09:45 AM
      Why no EMIB?David Hess2018/11/09 09:43 PM
        Why no EMIB?dmcq2018/11/10 07:35 AM
          Why no EMIB?Maynard Handley2018/11/10 09:27 AM
          Why no EMIB?David Hess2018/11/10 09:37 AM
  TTMDaniel B2018/11/06 02:21 PM
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