Sunny Cove wide

By: Travis Downs (travis.downs.delete@this.gmail.com), December 16, 2018 9:19 am
Room: Moderated Discussions
anon (spam.delete.delete.delete@this.this.this.spam.com) on December 15, 2018 9:55 am wrote:
> Travis Downs (travis.downs.delete@this.gmail.com) on December 15, 2018 9:08 am wrote:
> > anon (spam.delete.delete.delete@this.this.this.spam.com) on December 14, 2018 2:57 am wrote:
> > > Travis Downs (travis.downs.delete@this.gmail.com) on December 13, 2018 4:36 pm wrote:
> > > > anon (spam.delete.delete.delete@this.this.this.spam.com) on December 13, 2018 3:51 pm wrote:
> > > > >
> > > > > We're talking about x86, you can't have multiple flags so no
> > > > > matter how it's handled there's only one possible source.
> > > > >
> > > >
> > > > In the in-order part sure, but executing out of order of course there can be many different flag values
> > > > in flight at once. So flags have to be renamed just like registers or else out-of-order doesn't work.
> > > >
> > > > As far as I know the renamer associates writes of the flags to the same phys register as the destination
> > > > of the flag-writing instruction (and this means that something like test or cmp which doesn't have
> > > > a destination register still gets a renamed physical register, just for the flags). Every flag
> > > > consuming instruction then gets a reference to the last written flag register.
> > > >
> > > > That's at least what Intel describes in their patents: other variants are possible
> > > > but it appears to work reasonably close to this based on experimentation.
> > > >
> > >
> > > The point is that renaming works differently for flags.
> > > There aren't multiple flags to choose from. It's always the most recent one.
> >
> > Well there are multiple flags and instructions write different subsets of them, but sure it's
> > not exactly the same as register renaming because it's a somewhat more restricted problem
> > in that sense (although multiple flags can be written which is not true for registers).
> >
>
> Like I said partial register problems don't apply due to the macro fusion restrictions.
>
> > In any case, let's assume for the sake of argument that flag renaming is much simpler at the hardware
> > level (as I mentioned twice already I think it basically piggy-backs on the destination register
> > renaming). The original claim was that flag renaming doesn't occur and so test/jcc-type fusion was
> > therefore easier. I think we agree that flag renaming does occur, but that perhaps it is "easy",
> > so how does that relate to the original discussion? What does it say about fusing mov/op?
> >
>
> I'm not sure how you managed to interpret "there is only one most recent SR" as "there is no renaming".
> If there was only one SR the qualifier "most recent" would be redundant.

I was referring to this:

> Implicit operands like
> flags and with push/pop are dealt with in the frontend iirc so all the information is available.

I thought it meant "flags are not renamed" since they are handled entirely in the front-end which is how we started this long digression. If you believe that flags are renamed, but that this is simpler in hardware than general purpose register renaming, then we probably agree.

As before, I don't think the discussion of whether flags are renamed is even relevant to macro-fusion.

> And they are handled as always because the jump doesn't produce a result.
> This is about the result that is passed between the fused instructions.
> You must be able to recognize that there's a difference between passing SR results and GPR results.

Finally I think I understand the disconnect and why you keep talking about the renamer and "overwriting" registers and now passing results between the fused instructions.

As I understand now you see macro-fusion as still leaving the two component ops somehow intact although "fused together", so that the renamer, for example, still needs to handle the complexity of a mov followed by an op and that's how we started discussed this.

That is, that the result of macro-fusion is similar in a way to the result of micro-fusion: where both uops still exist, but are fused together for some (perhaps all) of the pipeline.

Seen in that context, this whole discussion makes sense.

However, I don't think that's how macro-fusion works at all. In my understanding, a single uop pops out of decoding, and from there on it looks exactly like any other single uop that could have originated from a single instruction. I.e., there is no trace of the "fusedness" of the instruction (except to the extent that the produced op obviously doesn't come from an ISA-visible instruction).

Seen in that light maybe what I'm saying is clearer: the decoder takes the mov-op pair and emits a single lea-like op for the rest of the pipeline, which doesn't retain any trace of its fused nature. There is no renaming problem because it looks like any other instruction with 2 inputs and 1 output.

Maybe we are on the same page now?
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TopicPosted ByDate
Sunny Cove wideSeni2018/12/12 02:58 PM
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                        Sunny Cove wideanon2018/12/15 10:55 AM
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        Sunny Cove wideSeni2018/12/13 04:20 PM
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          Sunny Cove wideanon³2018/12/13 10:34 PM
            Sunny Cove wideTravis Downs2018/12/16 07:53 PM
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