RISC-V inferior to ARMv8

By: Wilco (Wilco.dijkstra.delete@this.ntlworld.com), December 20, 2018 1:31 pm
Room: Moderated Discussions
Heikki Kultala (heikki.kultala.delete@this.tut.fi) on December 20, 2018 7:36 am wrote:
> I'm also not very enthustiastic about RISC-V.
>
> It fixes the stupidities of 1980's RISC architectures, but it's still way too typical RISC.
> And it is simply inferior ISA compared to ARMv8, which is much
> more pragmatic and includes many practical non-riscy features.
>
> I have not studied the system-level details (memory consistency, virtual memory etc.) of RISC-V,
> but for userspace code, things I mostly consider inferior in RISC-V compared to ARMv8 are:
>
> * Lacks any predicated instructions, even conditional moves.
>
> They say branch prediction is so good that we should do everything with branches,
> but unnecessary unpredictable branches just consume space in the branch prediction
> tables, worsening the accuracy for those branches that could be predicted.
>
> And then there is the Spectre thing. Even when we have good branch
> prediction, we should still minimize the number of branches
>
> * Lacks more complicated addressing modes.
>
> Load an integer from an array, RISC-V needs three instructions for that (shift, add, load).
> ARMv8 does that with SINGLE instruction. And loading a value from array is a VERY common thing.
>
> ARMv8 has also autoincrementing memory ops. These are also very nice thing to have for many situations.
>
> ARMv8 also has load pair and store pair, effectively doubling bandwidth between core and L1D.

I'd add small immediate ranges:

load/store +-2KB (half of range wasted due to being signed)
jump/call +-1MB (5 bits wasted so most calls need 2 instructions)
branch +-4KB (extra branch instructions required when a function is > 4KB)
add/sub +-2KB (need 3+ instructions for larger immediates)

Basic if-statements like if (x & 0xff0) require 4-5 instructions vs 2 on AArch64...

Wilco
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TopicPosted ByDate
RISC-V Summit ProceedingsGabriele Svelto2018/12/19 08:36 AM
  RISC-V gut feelingsKonrad Schwarz2018/12/20 04:30 AM
    RISC-V inferior to ARMv8Heikki Kultala2018/12/20 07:36 AM
      RISC-V inferior to ARMv8Wilco2018/12/20 01:31 PM
        RISC-V inferior to ARMv8Travis Downs2018/12/20 02:18 PM
          RISC-V inferior to ARMv8Wilco2018/12/21 03:43 AM
            RISC-V inferior to ARMv8Ronald Maas2018/12/21 09:35 AM
          RISC-V inferior to ARMv8juanrga2018/12/21 10:28 AM
            RISC-V inferior to ARMv8Maynard Handley2018/12/21 02:39 PM
              RISC-V inferior to ARMv8anon2018/12/21 03:38 PM
                RISC-V inferior to ARMv8juanrga2018/12/23 04:39 AM
                  With similar logic nor do frequency (NT)Megol2018/12/23 09:45 AM
              RISC-V inferior to ARMv8juanrga2018/12/23 04:44 AM
                RISC-V inferior to ARMv8Wilco2018/12/23 06:21 AM
      RISC-V inferior to ARMv8Michael S2018/12/20 03:24 PM
        RISC-V inferior to ARMv8anon2018/12/20 04:22 PM
          RISC-V inferior to ARMv8Travis Downs2018/12/21 06:16 PM
            RISC-V inferior to ARMv8anon2018/12/22 03:53 AM
              Execution runtimes and SpectreFoo_2018/12/22 06:02 AM
        RISC-V inferior to ARMv8Adrian2018/12/20 08:51 PM
          RISC-V inferior to ARMv8Doug S2018/12/20 11:10 PM
            RISC-V inferior to ARMv8Adrian2018/12/20 11:38 PM
              RISC-V inferior to ARMv8Michael S2018/12/21 02:31 AM
                RISC-V inferior to ARMv8Adrian2018/12/21 03:23 AM
            RISC-V inferior to ARMv8random person2018/12/21 02:04 AM
              RISC-V inferior to ARMv8dmcq2018/12/21 04:27 AM
              RISC-V inferior to ARMv8juanrga2018/12/21 10:36 AM
              RISC-V inferior to ARMv8Doug S2018/12/21 12:02 PM
            RISC-V inferior to ARMv8juanrga2018/12/21 10:23 AM
          RISC-V inferior to ARMv8Adrian2018/12/20 11:21 PM
          RISC-V inferior to ARMv8anon2018/12/21 01:48 AM
            RISC-V inferior to ARMv8Adrian2018/12/21 03:44 AM
              RISC-V inferior to ARMv8anon2018/12/21 05:24 AM
            RISC-V inferior to ARMv8Adrian2018/12/21 04:09 AM
              RISC-V inferior to ARMv8Wilco2018/12/21 04:28 AM
          RISC-V inferior to ARMv8Michael S2018/12/21 02:27 AM
            RISC-V inferior to ARMv8Gabriele Svelto2018/12/21 01:09 PM
              RISC-V inferior to ARMv8Maynard Handley2018/12/21 02:58 PM
              RISC-V inferior to ARMv8Wilco2018/12/21 03:43 PM
                RISC-V inferior to ARMv8Travis Downs2018/12/21 05:45 PM
                  RISC-V inferior to ARMv8Wilco2018/12/22 04:37 AM
                    RISC-V inferior to ARMv8Travis Downs2018/12/22 06:54 AM
                      RISC-V inferior to ARMv8Wilco2018/12/22 10:32 AM
                Cracking is not freeGabriele Svelto2018/12/22 02:09 AM
                  Cracking is not freeWilco2018/12/22 04:32 AM
                    Cracking is not freeTravis Downs2018/12/22 07:07 AM
                      Cracking is not freeWilco2018/12/22 07:38 AM
                        Cracking is not freeTravis Downs2018/12/22 07:47 AM
                          Cracking is not freeWilco2018/12/22 10:24 AM
                            Cracking is not freeTravis Downs2018/12/25 03:41 PM
                              Cracking is not freeanon.12018/12/25 08:14 PM
                        multi-instruction decode and renamePaul A. Clayton2018/12/22 06:45 PM
                    Cracking is not freeGabriele Svelto2018/12/22 12:30 PM
                      Cracking is not freeWilco2018/12/23 06:48 AM
                      Cracking is not freeMichael S2018/12/23 08:09 AM
                        Cracking is not freeGabriele Svelto2018/12/26 02:53 PM
          RISC-V inferior to ARMv8rwessel2018/12/21 01:13 PM
          RISC-V inferior to ARMv8Seni2018/12/21 02:33 PM
            RISC-V inferior to ARMv8Wilco2018/12/21 03:33 PM
              RISC-V inferior to ARMv8Travis Downs2018/12/21 05:49 PM
                RISC-V inferior to ARMv8Wilco2018/12/22 04:58 AM
                  RISC-V inferior to ARMv8Travis Downs2018/12/22 07:03 AM
                    RISC-V inferior to ARMv8Wilco2018/12/22 07:22 AM
                      RISC-V inferior to ARMv8Travis Downs2018/12/22 07:40 AM
        RISC-V inferior to ARMv8dmcq2018/12/21 03:57 AM
      RISC-V inferior to ARMv8Konrad Schwarz2018/12/21 02:25 AM
      RISC-V inferior to ARMv8j2018/12/21 10:46 AM
        RISC-V inferior to ARMv8Travis Downs2018/12/21 06:08 PM
          RISC-V inferior to ARMv8dmcq2018/12/22 07:45 AM
            RISC-V inferior to ARMv8Travis Downs2018/12/22 07:50 AM
              RISC-V inferior to ARMv8Michael S2018/12/22 08:15 AM
                RISC-V inferior to ARMv8dmcq2018/12/22 10:41 AM
        RISC-V inferior to ARMv8AnonQ2018/12/22 08:13 AM
    RISC-V gut feelingsdmcq2018/12/20 07:41 AM
      RISC-V initial takeKonrad Schwarz2018/12/21 02:17 AM
        RISC-V initial takedmcq2018/12/21 03:23 AM
      RISC-V gut feelingsMontaray Jack2018/12/22 02:56 PM
        RISC-V gut feelingsdmcq2018/12/23 04:38 AM
  RISC-V Summit Proceedingsjuanrga2018/12/21 10:47 AM
    RISC-V Summit Proceedingsdmcq2018/12/22 06:21 AM
      RISC-V Summit ProceedingsMontaray Jack2018/12/22 02:03 PM
        RISC-V Summit Proceedingsdmcq2018/12/23 04:39 AM
  RISC-V Summit Proceedingsanon22018/12/21 10:57 AM
    RISC-V Summit ProceedingsMichael S2018/12/22 08:36 AM
      RISC-V Summit ProceedingsAnon2018/12/22 05:51 PM
      Not Stanford MIPS but commercial MIPSPaul A. Clayton2018/12/23 03:05 AM
        Not Stanford MIPS but commercial MIPSMichael S2018/12/23 03:49 AM
        Not Stanford MIPS but commercial MIPSdmcq2018/12/23 04:52 AM
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