By: dmcq (dmcq.delete@this.fano.co.uk), December 21, 2018 3:23 am
Room: Moderated Discussions
Konrad Schwarz (no.spam.delete@this.no.spam) on December 21, 2018 2:17 am wrote:
> dmcq (dmcq.delete@this.fano.co.uk) on December 20, 2018 7:41 am wrote:
> > Konrad Schwarz (no.spam.delete@this.no.spam) on December 20, 2018 4:30 am wrote:
>
> > > * no cache management instructions, no cache architecture (caches are not self-describing)
> > > * no TLB management instructions
> > > * very limited fence instructions, unclear semantics
> > > * memory attributes are not stored in the paging tables, but in separate registers
> > > * no guidance on mapping the simple atomic memory operations to the system bus
> > > * no system bus definition (obviously related to the above)
> > >
> > > SiFive have defined a bus known as TileLink, but this has nowhere
> > > near the maturity of AXI/ACE, or of the PPC 60x bus definition
> >
> > I'd expect most users to use AMBA or CoreConnect or something like that unless they have very
> > special requirements.
>
> The raison d'être for RISC-V is lower-cost ASICs/SoCs. By not specifying
> a system bus/interconnect, interoperability is compromised and the market
> is needlessly fragmented (i.e., cores with AMBA and with TileLink exist).
I see the matter quite differently, there's lots of ip sold to the existing standards.
> The design of the interconnect has ramifications on the instruction set -- e.g., both ARM and
> IBM require the use of cache management/synchronization instructions as the system level interconnect
> is not coherent. RISC-V currently does not address this at all; any solutions are proprietary
> and may need to be rewritten if the core is replaced in a next gen design.
There's no great difference in the requirements at API level nowadays. One bus might be able to support things better than another but that can be a choice at implementation time.
> The atomic memory operations (AMO) are not supported by AMBA (in fairness, load locked/store
> conditional is also not supported on e.g. APB), even though they would be most useful there
> to enable/disable per device interupts, modify general-purpose outputs, etc. This means
> the AMO are mostly an evolutionary dead end if AMBA is going to be the solution.
ARMv8.2 has atomic memory operations and AMBA does support them. I'm not altogether sure why you think load locked/store conditional would be a good idea for a peripheral bus. Any such messing around should be done in the processor caches or system bus.
> dmcq (dmcq.delete@this.fano.co.uk) on December 20, 2018 7:41 am wrote:
> > Konrad Schwarz (no.spam.delete@this.no.spam) on December 20, 2018 4:30 am wrote:
>
> > > * no cache management instructions, no cache architecture (caches are not self-describing)
> > > * no TLB management instructions
> > > * very limited fence instructions, unclear semantics
> > > * memory attributes are not stored in the paging tables, but in separate registers
> > > * no guidance on mapping the simple atomic memory operations to the system bus
> > > * no system bus definition (obviously related to the above)
> > >
> > > SiFive have defined a bus known as TileLink, but this has nowhere
> > > near the maturity of AXI/ACE, or of the PPC 60x bus definition
> >
> > I'd expect most users to use AMBA or CoreConnect or something like that unless they have very
> > special requirements.
>
> The raison d'être for RISC-V is lower-cost ASICs/SoCs. By not specifying
> a system bus/interconnect, interoperability is compromised and the market
> is needlessly fragmented (i.e., cores with AMBA and with TileLink exist).
I see the matter quite differently, there's lots of ip sold to the existing standards.
> The design of the interconnect has ramifications on the instruction set -- e.g., both ARM and
> IBM require the use of cache management/synchronization instructions as the system level interconnect
> is not coherent. RISC-V currently does not address this at all; any solutions are proprietary
> and may need to be rewritten if the core is replaced in a next gen design.
There's no great difference in the requirements at API level nowadays. One bus might be able to support things better than another but that can be a choice at implementation time.
> The atomic memory operations (AMO) are not supported by AMBA (in fairness, load locked/store
> conditional is also not supported on e.g. APB), even though they would be most useful there
> to enable/disable per device interupts, modify general-purpose outputs, etc. This means
> the AMO are mostly an evolutionary dead end if AMBA is going to be the solution.
ARMv8.2 has atomic memory operations and AMBA does support them. I'm not altogether sure why you think load locked/store conditional would be a good idea for a peripheral bus. Any such messing around should be done in the processor caches or system bus.
Topic | Posted By | Date |
---|---|---|
RISC-V Summit Proceedings | Gabriele Svelto | 2018/12/19 08:36 AM |
RISC-V gut feelings | Konrad Schwarz | 2018/12/20 04:30 AM |
RISC-V inferior to ARMv8 | Heikki Kultala | 2018/12/20 07:36 AM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/20 01:31 PM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/20 02:18 PM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/21 03:43 AM |
RISC-V inferior to ARMv8 | Ronald Maas | 2018/12/21 09:35 AM |
RISC-V inferior to ARMv8 | juanrga | 2018/12/21 10:28 AM |
RISC-V inferior to ARMv8 | Maynard Handley | 2018/12/21 02:39 PM |
RISC-V inferior to ARMv8 | anon | 2018/12/21 03:38 PM |
RISC-V inferior to ARMv8 | juanrga | 2018/12/23 04:39 AM |
With similar logic nor do frequency (NT) | Megol | 2018/12/23 09:45 AM |
RISC-V inferior to ARMv8 | juanrga | 2018/12/23 04:44 AM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/23 06:21 AM |
RISC-V inferior to ARMv8 | Michael S | 2018/12/20 03:24 PM |
RISC-V inferior to ARMv8 | anon | 2018/12/20 04:22 PM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/21 06:16 PM |
RISC-V inferior to ARMv8 | anon | 2018/12/22 03:53 AM |
Execution runtimes and Spectre | Foo_ | 2018/12/22 06:02 AM |
RISC-V inferior to ARMv8 | Adrian | 2018/12/20 08:51 PM |
RISC-V inferior to ARMv8 | Doug S | 2018/12/20 11:10 PM |
RISC-V inferior to ARMv8 | Adrian | 2018/12/20 11:38 PM |
RISC-V inferior to ARMv8 | Michael S | 2018/12/21 02:31 AM |
RISC-V inferior to ARMv8 | Adrian | 2018/12/21 03:23 AM |
RISC-V inferior to ARMv8 | random person | 2018/12/21 02:04 AM |
RISC-V inferior to ARMv8 | dmcq | 2018/12/21 04:27 AM |
RISC-V inferior to ARMv8 | juanrga | 2018/12/21 10:36 AM |
RISC-V inferior to ARMv8 | Doug S | 2018/12/21 12:02 PM |
RISC-V inferior to ARMv8 | juanrga | 2018/12/21 10:23 AM |
RISC-V inferior to ARMv8 | Adrian | 2018/12/20 11:21 PM |
RISC-V inferior to ARMv8 | anon | 2018/12/21 01:48 AM |
RISC-V inferior to ARMv8 | Adrian | 2018/12/21 03:44 AM |
RISC-V inferior to ARMv8 | anon | 2018/12/21 05:24 AM |
RISC-V inferior to ARMv8 | Adrian | 2018/12/21 04:09 AM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/21 04:28 AM |
RISC-V inferior to ARMv8 | Michael S | 2018/12/21 02:27 AM |
RISC-V inferior to ARMv8 | Gabriele Svelto | 2018/12/21 01:09 PM |
RISC-V inferior to ARMv8 | Maynard Handley | 2018/12/21 02:58 PM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/21 03:43 PM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/21 05:45 PM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/22 04:37 AM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/22 06:54 AM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/22 10:32 AM |
Cracking is not free | Gabriele Svelto | 2018/12/22 02:09 AM |
Cracking is not free | Wilco | 2018/12/22 04:32 AM |
Cracking is not free | Travis Downs | 2018/12/22 07:07 AM |
Cracking is not free | Wilco | 2018/12/22 07:38 AM |
Cracking is not free | Travis Downs | 2018/12/22 07:47 AM |
Cracking is not free | Wilco | 2018/12/22 10:24 AM |
Cracking is not free | Travis Downs | 2018/12/25 03:41 PM |
Cracking is not free | anon.1 | 2018/12/25 08:14 PM |
multi-instruction decode and rename | Paul A. Clayton | 2018/12/22 06:45 PM |
Cracking is not free | Gabriele Svelto | 2018/12/22 12:30 PM |
Cracking is not free | Wilco | 2018/12/23 06:48 AM |
Cracking is not free | Michael S | 2018/12/23 08:09 AM |
Cracking is not free | Gabriele Svelto | 2018/12/26 02:53 PM |
RISC-V inferior to ARMv8 | rwessel | 2018/12/21 01:13 PM |
RISC-V inferior to ARMv8 | Seni | 2018/12/21 02:33 PM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/21 03:33 PM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/21 05:49 PM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/22 04:58 AM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/22 07:03 AM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/22 07:22 AM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/22 07:40 AM |
RISC-V inferior to ARMv8 | dmcq | 2018/12/21 03:57 AM |
RISC-V inferior to ARMv8 | Konrad Schwarz | 2018/12/21 02:25 AM |
RISC-V inferior to ARMv8 | j | 2018/12/21 10:46 AM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/21 06:08 PM |
RISC-V inferior to ARMv8 | dmcq | 2018/12/22 07:45 AM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/22 07:50 AM |
RISC-V inferior to ARMv8 | Michael S | 2018/12/22 08:15 AM |
RISC-V inferior to ARMv8 | dmcq | 2018/12/22 10:41 AM |
RISC-V inferior to ARMv8 | AnonQ | 2018/12/22 08:13 AM |
RISC-V gut feelings | dmcq | 2018/12/20 07:41 AM |
RISC-V initial take | Konrad Schwarz | 2018/12/21 02:17 AM |
RISC-V initial take | dmcq | 2018/12/21 03:23 AM |
RISC-V gut feelings | Montaray Jack | 2018/12/22 02:56 PM |
RISC-V gut feelings | dmcq | 2018/12/23 04:38 AM |
RISC-V Summit Proceedings | juanrga | 2018/12/21 10:47 AM |
RISC-V Summit Proceedings | dmcq | 2018/12/22 06:21 AM |
RISC-V Summit Proceedings | Montaray Jack | 2018/12/22 02:03 PM |
RISC-V Summit Proceedings | dmcq | 2018/12/23 04:39 AM |
RISC-V Summit Proceedings | anon2 | 2018/12/21 10:57 AM |
RISC-V Summit Proceedings | Michael S | 2018/12/22 08:36 AM |
RISC-V Summit Proceedings | Anon | 2018/12/22 05:51 PM |
Not Stanford MIPS but commercial MIPS | Paul A. Clayton | 2018/12/23 03:05 AM |
Not Stanford MIPS but commercial MIPS | Michael S | 2018/12/23 03:49 AM |
Not Stanford MIPS but commercial MIPS | dmcq | 2018/12/23 04:52 AM |