RISC-V inferior to ARMv8

By: anon (spam.delete.delete.delete@this.this.this.spam.com), December 21, 2018 5:24 am
Room: Moderated Discussions
Adrian (a.delete@this.acm.org) on December 21, 2018 3:44 am wrote:
> > > anon (spam.delete.delete.delete@this.this.this.spam.com) on December 21, 2018 1:48 am
> >
> > In your experience how many of the loops with a fixed increment/decrement
> > do not have a counter that could be used for the adresses?
> > Also I'm not sure if works for absolutely any kind of loop, if you're
> > not working with a fixed stride you're going to have a problem.
> On the IBM 801 & POWER CPUs, you have to use the addressing modes with update, because the loop
> counter is usually not a general purpose register, so you cannot use it in address computation.

Obviously that's not going to happen on RISC-V, but I can see where you're coming from.

> On x86, where you do not have addressing modes with update, but where you can
> compute base + index * shift, obviously you normally use the loop counter.
> That is why I have already said that this is an acceptable alternative for the IBM 801 addressing modes.
> Nevertheless, using the loop counter is less general. If you can reorganize your data structures, you can bring
> them to a form, e.g. a structure of arrays, which is convenient for addressing using the loop counter. This
> is not an important restriction, because such a data organization is also preferable for other reasons.

Exactly. I mean the shift also assumes your data type length is a power of two, but if it's not you'll be running into a lot of problems anyway.

> If you are not allowed to reorganize the data structures, there are
> cases when you have to add extra address computation instructions.

Yes, on the flipside if it does work you save one register compared to autoincrement. It's a bit of a tradeoff.
Considering that RISC-V is supposed to run on low end embedded CPUs with 16 registers and their general aversion to breaking with the 2 in 1 out pattern I'd say shifted index is probably a better fit than register autoincrement, but I guess either one would work.

> On processors where you cannot shift the index, but you can still add a base and an index,
> you can avoid adding instructions for address computation only if the loop accesses a single
> array or the loop accesses multiple arrays, but whose elements have all the same size.

Yes, but at least it's better than not having anything.

[Merging the other post]
> Sorry, I did not reply to one of your points about the "fixed increment/decrement", the IBM 801 and
> also POWER addressing modes compute base + index for addressing the operand of load/store, then they
> update the base register with the result. The index value can be immediate or from a register.

Yeah, I assumed you were talking just about the simple immediate autoincrement that ARM copied, but the more general register form does obviously cover all cases.
Still there's the tradeoff of not being able to use the counter in cases where shifted index could. I'd say both adress all possible scenarios, register autoincrement handles the cases where you don't need the counter or where it's not shift compatible but still needed better, while shifted index handles the "nice" cases better. Maybe I'm a bit biased due to trying to write "nice" code that benefits more from the shifted index variant, but for an implementation I'd prefer it since it doesn't have to write to two registers.

Either way both solve the problem and even reduced versions (e.g. just immediate autoincrement or base + index reg) which really shouldn't be difficult to implement would cover a lot of cases.

> So the innovation of these addressing modes (compared to older auto-decrement or auto-increment
> modes) is precisely that they are also applicable for loops where the increment/decrement
> is not fixed, which happens frequently for data organized as arrays of structures.
> The alternative approach, as mentioned in the other reply, is to reorganize the data in a way that
> is suitable for addressing using the loop counter, when the modes with update are not needed.
> While IBM 801 & POWER use only pre-indexing, to keep the implementation simple, other followers,
> e.g. the original ARM, also have post-indexing. 64-bit ARM allows both pre-indexing and post-indexing
> only in few instructions, presumably for an easier implementation than in 32-bit ARM.

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TopicPosted ByDate
RISC-V Summit ProceedingsGabriele Svelto2018/12/19 08:36 AM
  RISC-V gut feelingsKonrad Schwarz2018/12/20 04:30 AM
    RISC-V inferior to ARMv8Heikki Kultala2018/12/20 07:36 AM
      RISC-V inferior to ARMv8Wilco2018/12/20 01:31 PM
        RISC-V inferior to ARMv8Travis Downs2018/12/20 02:18 PM
          RISC-V inferior to ARMv8Wilco2018/12/21 03:43 AM
            RISC-V inferior to ARMv8Ronald Maas2018/12/21 09:35 AM
          RISC-V inferior to ARMv8juanrga2018/12/21 10:28 AM
            RISC-V inferior to ARMv8Maynard Handley2018/12/21 02:39 PM
              RISC-V inferior to ARMv8anon2018/12/21 03:38 PM
                RISC-V inferior to ARMv8juanrga2018/12/23 04:39 AM
                  With similar logic nor do frequency (NT)Megol2018/12/23 09:45 AM
              RISC-V inferior to ARMv8juanrga2018/12/23 04:44 AM
                RISC-V inferior to ARMv8Wilco2018/12/23 06:21 AM
      RISC-V inferior to ARMv8Michael S2018/12/20 03:24 PM
        RISC-V inferior to ARMv8anon2018/12/20 04:22 PM
          RISC-V inferior to ARMv8Travis Downs2018/12/21 06:16 PM
            RISC-V inferior to ARMv8anon2018/12/22 03:53 AM
              Execution runtimes and SpectreFoo_2018/12/22 06:02 AM
        RISC-V inferior to ARMv8Adrian2018/12/20 08:51 PM
          RISC-V inferior to ARMv8Doug S2018/12/20 11:10 PM
            RISC-V inferior to ARMv8Adrian2018/12/20 11:38 PM
              RISC-V inferior to ARMv8Michael S2018/12/21 02:31 AM
                RISC-V inferior to ARMv8Adrian2018/12/21 03:23 AM
            RISC-V inferior to ARMv8random person2018/12/21 02:04 AM
              RISC-V inferior to ARMv8dmcq2018/12/21 04:27 AM
              RISC-V inferior to ARMv8juanrga2018/12/21 10:36 AM
              RISC-V inferior to ARMv8Doug S2018/12/21 12:02 PM
            RISC-V inferior to ARMv8juanrga2018/12/21 10:23 AM
          RISC-V inferior to ARMv8Adrian2018/12/20 11:21 PM
          RISC-V inferior to ARMv8anon2018/12/21 01:48 AM
            RISC-V inferior to ARMv8Adrian2018/12/21 03:44 AM
              RISC-V inferior to ARMv8anon2018/12/21 05:24 AM
            RISC-V inferior to ARMv8Adrian2018/12/21 04:09 AM
              RISC-V inferior to ARMv8Wilco2018/12/21 04:28 AM
          RISC-V inferior to ARMv8Michael S2018/12/21 02:27 AM
            RISC-V inferior to ARMv8Gabriele Svelto2018/12/21 01:09 PM
              RISC-V inferior to ARMv8Maynard Handley2018/12/21 02:58 PM
              RISC-V inferior to ARMv8Wilco2018/12/21 03:43 PM
                RISC-V inferior to ARMv8Travis Downs2018/12/21 05:45 PM
                  RISC-V inferior to ARMv8Wilco2018/12/22 04:37 AM
                    RISC-V inferior to ARMv8Travis Downs2018/12/22 06:54 AM
                      RISC-V inferior to ARMv8Wilco2018/12/22 10:32 AM
                Cracking is not freeGabriele Svelto2018/12/22 02:09 AM
                  Cracking is not freeWilco2018/12/22 04:32 AM
                    Cracking is not freeTravis Downs2018/12/22 07:07 AM
                      Cracking is not freeWilco2018/12/22 07:38 AM
                        Cracking is not freeTravis Downs2018/12/22 07:47 AM
                          Cracking is not freeWilco2018/12/22 10:24 AM
                            Cracking is not freeTravis Downs2018/12/25 03:41 PM
                              Cracking is not freeanon.12018/12/25 08:14 PM
                        multi-instruction decode and renamePaul A. Clayton2018/12/22 06:45 PM
                    Cracking is not freeGabriele Svelto2018/12/22 12:30 PM
                      Cracking is not freeWilco2018/12/23 06:48 AM
                      Cracking is not freeMichael S2018/12/23 08:09 AM
                        Cracking is not freeGabriele Svelto2018/12/26 02:53 PM
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          RISC-V inferior to ARMv8Seni2018/12/21 02:33 PM
            RISC-V inferior to ARMv8Wilco2018/12/21 03:33 PM
              RISC-V inferior to ARMv8Travis Downs2018/12/21 05:49 PM
                RISC-V inferior to ARMv8Wilco2018/12/22 04:58 AM
                  RISC-V inferior to ARMv8Travis Downs2018/12/22 07:03 AM
                    RISC-V inferior to ARMv8Wilco2018/12/22 07:22 AM
                      RISC-V inferior to ARMv8Travis Downs2018/12/22 07:40 AM
        RISC-V inferior to ARMv8dmcq2018/12/21 03:57 AM
      RISC-V inferior to ARMv8Konrad Schwarz2018/12/21 02:25 AM
      RISC-V inferior to ARMv8j2018/12/21 10:46 AM
        RISC-V inferior to ARMv8Travis Downs2018/12/21 06:08 PM
          RISC-V inferior to ARMv8dmcq2018/12/22 07:45 AM
            RISC-V inferior to ARMv8Travis Downs2018/12/22 07:50 AM
              RISC-V inferior to ARMv8Michael S2018/12/22 08:15 AM
                RISC-V inferior to ARMv8dmcq2018/12/22 10:41 AM
        RISC-V inferior to ARMv8AnonQ2018/12/22 08:13 AM
    RISC-V gut feelingsdmcq2018/12/20 07:41 AM
      RISC-V initial takeKonrad Schwarz2018/12/21 02:17 AM
        RISC-V initial takedmcq2018/12/21 03:23 AM
      RISC-V gut feelingsMontaray Jack2018/12/22 02:56 PM
        RISC-V gut feelingsdmcq2018/12/23 04:38 AM
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    RISC-V Summit Proceedingsdmcq2018/12/22 06:21 AM
      RISC-V Summit ProceedingsMontaray Jack2018/12/22 02:03 PM
        RISC-V Summit Proceedingsdmcq2018/12/23 04:39 AM
  RISC-V Summit Proceedingsanon22018/12/21 10:57 AM
    RISC-V Summit ProceedingsMichael S2018/12/22 08:36 AM
      RISC-V Summit ProceedingsAnon2018/12/22 05:51 PM
      Not Stanford MIPS but commercial MIPSPaul A. Clayton2018/12/23 03:05 AM
        Not Stanford MIPS but commercial MIPSMichael S2018/12/23 03:49 AM
        Not Stanford MIPS but commercial MIPSdmcq2018/12/23 04:52 AM
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