Wilco (Wilco.dijkstra.delete@this.ntlworld.com) on December 21, 2018 3:43 am wrote:
> Travis Downs (travis.downs.delete@this.gmail.com) on December 20, 2018 2:18 pm wrote:
> > I largely agree on ISA design - it's too simple for its own good when it
> > comes to high-perf designs, but I think it all mostly doesn't matter.
> >
> > If RISC-V succeeds, it will be because it is free, both in $ terms
> > and in the ability to use the designs and ISA royalty free.
> >
> > Price matters most at the ultra low-end of the market where speeds are usually measured in the single
> > to triple-digit MHz. The mentioned differences might make 10% to 50% difference in performance,
> > but these low-end designs already range by a factor of 10x in performance fairly easily.
> >
> > At this very low end the simplicity probably helps overall, even if it hurts performance.
>
> And that would cost you in power too. However the real cost at the low end is code density
> given code runs from on-chip flash and SRAM. Historically MIPS was the worst ISA for codesize
> - MIPS16 compressed codesize was larger than 32-bit ARM! RISC-V is even more basic and reduces
> all immediate offsets, thus requiring far more instructions for the same task.
>
> Wilco

Code density of RISC-V is actually pretty good. RISC-V 32-bit compressed requires slightly more bytes compared to ARM Thumb2. But as Thumb2 instruction encoding is highly irregular, it requires significant more transistors to decode. And more active transistors requires more power.

This is applicable for low end designs only. Once you go up the performance scale, the difference of having auto-increment addressing or not will drop below the noise floor.

I agree with Travis that other factors are far more important in the overall decision process. E.g. cost, flexibility to implement custom instructions, availability of tools and support, maturity of the ISA and the organization behind it, etc.

Ronald