RISC-V inferior to ARMv8

By: Travis Downs (travis.downs.delete@this.gmail.com), December 21, 2018 6:45 pm
Room: Moderated Discussions
Wilco (Wilco.dijkstra.delete@this.ntlworld.com) on December 21, 2018 3:43 pm wrote:
> That's not true - besides reducing I-cache misses, you also get a wider decode and rename for
> free.

Agreed about decode to some extent (it may not be exactly free if the decoder has to do the cracking), but as far as rename goes, doesn't cracking generally occur before rename, generally at or around decode? So by the time the ops hit the renamer you haven't saved anything vs two separate instructions.
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TopicPosted ByDate
RISC-V Summit ProceedingsGabriele Svelto2018/12/19 09:36 AM
  RISC-V gut feelingsKonrad Schwarz2018/12/20 05:30 AM
    RISC-V inferior to ARMv8Heikki Kultala2018/12/20 08:36 AM
      RISC-V inferior to ARMv8Wilco2018/12/20 02:31 PM
        RISC-V inferior to ARMv8Travis Downs2018/12/20 03:18 PM
          RISC-V inferior to ARMv8Wilco2018/12/21 04:43 AM
            RISC-V inferior to ARMv8Ronald Maas2018/12/21 10:35 AM
          RISC-V inferior to ARMv8juanrga2018/12/21 11:28 AM
            RISC-V inferior to ARMv8Maynard Handley2018/12/21 03:39 PM
              RISC-V inferior to ARMv8anon2018/12/21 04:38 PM
                RISC-V inferior to ARMv8juanrga2018/12/23 05:39 AM
                  With similar logic nor do frequency (NT)Megol2018/12/23 10:45 AM
              RISC-V inferior to ARMv8juanrga2018/12/23 05:44 AM
                RISC-V inferior to ARMv8Wilco2018/12/23 07:21 AM
      RISC-V inferior to ARMv8Michael S2018/12/20 04:24 PM
        RISC-V inferior to ARMv8anon2018/12/20 05:22 PM
          RISC-V inferior to ARMv8Travis Downs2018/12/21 07:16 PM
            RISC-V inferior to ARMv8anon2018/12/22 04:53 AM
              Execution runtimes and SpectreFoo_2018/12/22 07:02 AM
        RISC-V inferior to ARMv8Adrian2018/12/20 09:51 PM
          RISC-V inferior to ARMv8Doug S2018/12/21 12:10 AM
            RISC-V inferior to ARMv8Adrian2018/12/21 12:38 AM
              RISC-V inferior to ARMv8Michael S2018/12/21 03:31 AM
                RISC-V inferior to ARMv8Adrian2018/12/21 04:23 AM
            RISC-V inferior to ARMv8random person2018/12/21 03:04 AM
              RISC-V inferior to ARMv8dmcq2018/12/21 05:27 AM
              RISC-V inferior to ARMv8juanrga2018/12/21 11:36 AM
              RISC-V inferior to ARMv8Doug S2018/12/21 01:02 PM
            RISC-V inferior to ARMv8juanrga2018/12/21 11:23 AM
          RISC-V inferior to ARMv8Adrian2018/12/21 12:21 AM
          RISC-V inferior to ARMv8anon2018/12/21 02:48 AM
            RISC-V inferior to ARMv8Adrian2018/12/21 04:44 AM
              RISC-V inferior to ARMv8anon2018/12/21 06:24 AM
            RISC-V inferior to ARMv8Adrian2018/12/21 05:09 AM
              RISC-V inferior to ARMv8Wilco2018/12/21 05:28 AM
          RISC-V inferior to ARMv8Michael S2018/12/21 03:27 AM
            RISC-V inferior to ARMv8Gabriele Svelto2018/12/21 02:09 PM
              RISC-V inferior to ARMv8Maynard Handley2018/12/21 03:58 PM
              RISC-V inferior to ARMv8Wilco2018/12/21 04:43 PM
                RISC-V inferior to ARMv8Travis Downs2018/12/21 06:45 PM
                  RISC-V inferior to ARMv8Wilco2018/12/22 05:37 AM
                    RISC-V inferior to ARMv8Travis Downs2018/12/22 07:54 AM
                      RISC-V inferior to ARMv8Wilco2018/12/22 11:32 AM
                Cracking is not freeGabriele Svelto2018/12/22 03:09 AM
                  Cracking is not freeWilco2018/12/22 05:32 AM
                    Cracking is not freeTravis Downs2018/12/22 08:07 AM
                      Cracking is not freeWilco2018/12/22 08:38 AM
                        Cracking is not freeTravis Downs2018/12/22 08:47 AM
                          Cracking is not freeWilco2018/12/22 11:24 AM
                            Cracking is not freeTravis Downs2018/12/25 04:41 PM
                              Cracking is not freeanon.12018/12/25 09:14 PM
                        multi-instruction decode and renamePaul A. Clayton2018/12/22 07:45 PM
                    Cracking is not freeGabriele Svelto2018/12/22 01:30 PM
                      Cracking is not freeWilco2018/12/23 07:48 AM
                      Cracking is not freeMichael S2018/12/23 09:09 AM
                        Cracking is not freeGabriele Svelto2018/12/26 03:53 PM
          RISC-V inferior to ARMv8rwessel2018/12/21 02:13 PM
          RISC-V inferior to ARMv8Seni2018/12/21 03:33 PM
            RISC-V inferior to ARMv8Wilco2018/12/21 04:33 PM
              RISC-V inferior to ARMv8Travis Downs2018/12/21 06:49 PM
                RISC-V inferior to ARMv8Wilco2018/12/22 05:58 AM
                  RISC-V inferior to ARMv8Travis Downs2018/12/22 08:03 AM
                    RISC-V inferior to ARMv8Wilco2018/12/22 08:22 AM
                      RISC-V inferior to ARMv8Travis Downs2018/12/22 08:40 AM
        RISC-V inferior to ARMv8dmcq2018/12/21 04:57 AM
      RISC-V inferior to ARMv8Konrad Schwarz2018/12/21 03:25 AM
      RISC-V inferior to ARMv8j2018/12/21 11:46 AM
        RISC-V inferior to ARMv8Travis Downs2018/12/21 07:08 PM
          RISC-V inferior to ARMv8dmcq2018/12/22 08:45 AM
            RISC-V inferior to ARMv8Travis Downs2018/12/22 08:50 AM
              RISC-V inferior to ARMv8Michael S2018/12/22 09:15 AM
                RISC-V inferior to ARMv8dmcq2018/12/22 11:41 AM
        RISC-V inferior to ARMv8AnonQ2018/12/22 09:13 AM
    RISC-V gut feelingsdmcq2018/12/20 08:41 AM
      RISC-V initial takeKonrad Schwarz2018/12/21 03:17 AM
        RISC-V initial takedmcq2018/12/21 04:23 AM
      RISC-V gut feelingsMontaray Jack2018/12/22 03:56 PM
        RISC-V gut feelingsdmcq2018/12/23 05:38 AM
  RISC-V Summit Proceedingsjuanrga2018/12/21 11:47 AM
    RISC-V Summit Proceedingsdmcq2018/12/22 07:21 AM
      RISC-V Summit ProceedingsMontaray Jack2018/12/22 03:03 PM
        RISC-V Summit Proceedingsdmcq2018/12/23 05:39 AM
  RISC-V Summit Proceedingsanon22018/12/21 11:57 AM
    RISC-V Summit ProceedingsMichael S2018/12/22 09:36 AM
      RISC-V Summit ProceedingsAnon2018/12/22 06:51 PM
      Not Stanford MIPS but commercial MIPSPaul A. Clayton2018/12/23 04:05 AM
        Not Stanford MIPS but commercial MIPSMichael S2018/12/23 04:49 AM
        Not Stanford MIPS but commercial MIPSdmcq2018/12/23 05:52 AM
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