RISC-V inferior to ARMv8

By: Travis Downs (travis.downs.delete@this.gmail.com), December 22, 2018 7:03 am
Room: Moderated Discussions
Wilco (Wilco.dijkstra.delete@this.ntlworld.com) on December 22, 2018 4:58 am wrote:
> Travis Downs (travis.downs.delete@this.gmail.com) on December 21, 2018 5:49 pm wrote:
> > Wilco (Wilco.dijkstra.delete@this.ntlworld.com) on December 21, 2018 3:33 pm wrote:
> >
> > > You have a dependency in both cases. However autoincrement actually gives fewer
> > > dependencies and enables more reordering between different accesses.
> >
> > Can you elaborate? Yes, there is (at least one) dependency chain in both cases, but in the loop
> > counter + indexing case there is only a single dependency chain associated with the loop counter,
> > and all the accesses hang off that chain (they aren't part of any carried chain).
> >
> > In the auto-increment case, each access that uses auto-increment forms a new dependency chain,
> > so for a loop with N accesses you'll have N carried dependency chains (and possibly the loop
> > counter chain as well if you are still using a loop counter). I'm struggling to see that
> > is "fewer dependencies and enables more reordering between different accesses".
>
> If you have N accesses and say 2 autoincrements split evenly you'd get 2 chains of size N/2
> which would be independent of each other if there are no other dependencies. Now this would
> be equally fast on most OoO cores. However on a core with partitioned resources (eg. POWER
> 9) it would be able to run the 2 chains in the partitions independently while the single increment
> case has more dependencies and slows down due to cross-partition penalties.

Sure, introducing additional dependencies for the sake of partitioning on such uarches might speed things up if everything gets grouped correctly, but that's very different than the original claim of fewer dependencies and more reordering. You can of course use two loop counters or whatever if you want two separate (but just as long) dependency chains on such an architecture.

Certainly it doesn't help on most OoO arches.

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TopicPosted ByDate
RISC-V Summit ProceedingsGabriele Svelto2018/12/19 08:36 AM
  RISC-V gut feelingsKonrad Schwarz2018/12/20 04:30 AM
    RISC-V inferior to ARMv8Heikki Kultala2018/12/20 07:36 AM
      RISC-V inferior to ARMv8Wilco2018/12/20 01:31 PM
        RISC-V inferior to ARMv8Travis Downs2018/12/20 02:18 PM
          RISC-V inferior to ARMv8Wilco2018/12/21 03:43 AM
            RISC-V inferior to ARMv8Ronald Maas2018/12/21 09:35 AM
          RISC-V inferior to ARMv8juanrga2018/12/21 10:28 AM
            RISC-V inferior to ARMv8Maynard Handley2018/12/21 02:39 PM
              RISC-V inferior to ARMv8anon2018/12/21 03:38 PM
                RISC-V inferior to ARMv8juanrga2018/12/23 04:39 AM
                  With similar logic nor do frequency (NT)Megol2018/12/23 09:45 AM
              RISC-V inferior to ARMv8juanrga2018/12/23 04:44 AM
                RISC-V inferior to ARMv8Wilco2018/12/23 06:21 AM
      RISC-V inferior to ARMv8Michael S2018/12/20 03:24 PM
        RISC-V inferior to ARMv8anon2018/12/20 04:22 PM
          RISC-V inferior to ARMv8Travis Downs2018/12/21 06:16 PM
            RISC-V inferior to ARMv8anon2018/12/22 03:53 AM
              Execution runtimes and SpectreFoo_2018/12/22 06:02 AM
        RISC-V inferior to ARMv8Adrian2018/12/20 08:51 PM
          RISC-V inferior to ARMv8Doug S2018/12/20 11:10 PM
            RISC-V inferior to ARMv8Adrian2018/12/20 11:38 PM
              RISC-V inferior to ARMv8Michael S2018/12/21 02:31 AM
                RISC-V inferior to ARMv8Adrian2018/12/21 03:23 AM
            RISC-V inferior to ARMv8random person2018/12/21 02:04 AM
              RISC-V inferior to ARMv8dmcq2018/12/21 04:27 AM
              RISC-V inferior to ARMv8juanrga2018/12/21 10:36 AM
              RISC-V inferior to ARMv8Doug S2018/12/21 12:02 PM
            RISC-V inferior to ARMv8juanrga2018/12/21 10:23 AM
          RISC-V inferior to ARMv8Adrian2018/12/20 11:21 PM
          RISC-V inferior to ARMv8anon2018/12/21 01:48 AM
            RISC-V inferior to ARMv8Adrian2018/12/21 03:44 AM
              RISC-V inferior to ARMv8anon2018/12/21 05:24 AM
            RISC-V inferior to ARMv8Adrian2018/12/21 04:09 AM
              RISC-V inferior to ARMv8Wilco2018/12/21 04:28 AM
          RISC-V inferior to ARMv8Michael S2018/12/21 02:27 AM
            RISC-V inferior to ARMv8Gabriele Svelto2018/12/21 01:09 PM
              RISC-V inferior to ARMv8Maynard Handley2018/12/21 02:58 PM
              RISC-V inferior to ARMv8Wilco2018/12/21 03:43 PM
                RISC-V inferior to ARMv8Travis Downs2018/12/21 05:45 PM
                  RISC-V inferior to ARMv8Wilco2018/12/22 04:37 AM
                    RISC-V inferior to ARMv8Travis Downs2018/12/22 06:54 AM
                      RISC-V inferior to ARMv8Wilco2018/12/22 10:32 AM
                Cracking is not freeGabriele Svelto2018/12/22 02:09 AM
                  Cracking is not freeWilco2018/12/22 04:32 AM
                    Cracking is not freeTravis Downs2018/12/22 07:07 AM
                      Cracking is not freeWilco2018/12/22 07:38 AM
                        Cracking is not freeTravis Downs2018/12/22 07:47 AM
                          Cracking is not freeWilco2018/12/22 10:24 AM
                            Cracking is not freeTravis Downs2018/12/25 03:41 PM
                              Cracking is not freeanon.12018/12/25 08:14 PM
                        multi-instruction decode and renamePaul A. Clayton2018/12/22 06:45 PM
                    Cracking is not freeGabriele Svelto2018/12/22 12:30 PM
                      Cracking is not freeWilco2018/12/23 06:48 AM
                      Cracking is not freeMichael S2018/12/23 08:09 AM
                        Cracking is not freeGabriele Svelto2018/12/26 02:53 PM
          RISC-V inferior to ARMv8rwessel2018/12/21 01:13 PM
          RISC-V inferior to ARMv8Seni2018/12/21 02:33 PM
            RISC-V inferior to ARMv8Wilco2018/12/21 03:33 PM
              RISC-V inferior to ARMv8Travis Downs2018/12/21 05:49 PM
                RISC-V inferior to ARMv8Wilco2018/12/22 04:58 AM
                  RISC-V inferior to ARMv8Travis Downs2018/12/22 07:03 AM
                    RISC-V inferior to ARMv8Wilco2018/12/22 07:22 AM
                      RISC-V inferior to ARMv8Travis Downs2018/12/22 07:40 AM
        RISC-V inferior to ARMv8dmcq2018/12/21 03:57 AM
      RISC-V inferior to ARMv8Konrad Schwarz2018/12/21 02:25 AM
      RISC-V inferior to ARMv8j2018/12/21 10:46 AM
        RISC-V inferior to ARMv8Travis Downs2018/12/21 06:08 PM
          RISC-V inferior to ARMv8dmcq2018/12/22 07:45 AM
            RISC-V inferior to ARMv8Travis Downs2018/12/22 07:50 AM
              RISC-V inferior to ARMv8Michael S2018/12/22 08:15 AM
                RISC-V inferior to ARMv8dmcq2018/12/22 10:41 AM
        RISC-V inferior to ARMv8AnonQ2018/12/22 08:13 AM
    RISC-V gut feelingsdmcq2018/12/20 07:41 AM
      RISC-V initial takeKonrad Schwarz2018/12/21 02:17 AM
        RISC-V initial takedmcq2018/12/21 03:23 AM
      RISC-V gut feelingsMontaray Jack2018/12/22 02:56 PM
        RISC-V gut feelingsdmcq2018/12/23 04:38 AM
  RISC-V Summit Proceedingsjuanrga2018/12/21 10:47 AM
    RISC-V Summit Proceedingsdmcq2018/12/22 06:21 AM
      RISC-V Summit ProceedingsMontaray Jack2018/12/22 02:03 PM
        RISC-V Summit Proceedingsdmcq2018/12/23 04:39 AM
  RISC-V Summit Proceedingsanon22018/12/21 10:57 AM
    RISC-V Summit ProceedingsMichael S2018/12/22 08:36 AM
      RISC-V Summit ProceedingsAnon2018/12/22 05:51 PM
      Not Stanford MIPS but commercial MIPSPaul A. Clayton2018/12/23 03:05 AM
        Not Stanford MIPS but commercial MIPSMichael S2018/12/23 03:49 AM
        Not Stanford MIPS but commercial MIPSdmcq2018/12/23 04:52 AM
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