By: Michael S (already5chosen.delete@this.yahoo.com), December 22, 2018 9:36 am
Room: Moderated Discussions
anon2 (anon.delete@this.anon.com) on December 21, 2018 10:57 am wrote:
> Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on December 19, 2018 8:36 am wrote:
> > The Inaugural RISC-V summit proceedings are available. As
> > usual with RISC-V workshops there's a lot of stuff in there.
>
> The Patterson talk was weird. He goes on for a long time on the benefits of RISC, and then
> starts describing the Google TPU as a great new CPU, but which is a .... CISC design.
>
>
> https://content.riscv.org/wp-content/uploads/2018/12/A-New-Golden-Age-for-Computer-Architecture-History-Challenges-and-Opportunities-David-Patterson-.pdf
I am not sure how lucid he still is.
Couple of years ago he said that RISC-V is a direct successor of Berkeley RISC tradition, when in fact anybody an see that RISV-V is a very close derivative of Stanford MIPS and has as little in common with earlier Berkeley RISCs as two RISC ISA possible can.
Considering that he is only 71 it is strange.
> Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on December 19, 2018 8:36 am wrote:
> > The Inaugural RISC-V summit proceedings are available. As
> > usual with RISC-V workshops there's a lot of stuff in there.
>
> The Patterson talk was weird. He goes on for a long time on the benefits of RISC, and then
> starts describing the Google TPU as a great new CPU, but which is a .... CISC design.
>
>
> https://content.riscv.org/wp-content/uploads/2018/12/A-New-Golden-Age-for-Computer-Architecture-History-Challenges-and-Opportunities-David-Patterson-.pdf
I am not sure how lucid he still is.
Couple of years ago he said that RISC-V is a direct successor of Berkeley RISC tradition, when in fact anybody an see that RISV-V is a very close derivative of Stanford MIPS and has as little in common with earlier Berkeley RISCs as two RISC ISA possible can.
Considering that he is only 71 it is strange.
Topic | Posted By | Date |
---|---|---|
RISC-V Summit Proceedings | Gabriele Svelto | 2018/12/19 09:36 AM |
RISC-V gut feelings | Konrad Schwarz | 2018/12/20 05:30 AM |
RISC-V inferior to ARMv8 | Heikki Kultala | 2018/12/20 08:36 AM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/20 02:31 PM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/20 03:18 PM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/21 04:43 AM |
RISC-V inferior to ARMv8 | Ronald Maas | 2018/12/21 10:35 AM |
RISC-V inferior to ARMv8 | juanrga | 2018/12/21 11:28 AM |
RISC-V inferior to ARMv8 | Maynard Handley | 2018/12/21 03:39 PM |
RISC-V inferior to ARMv8 | anon | 2018/12/21 04:38 PM |
RISC-V inferior to ARMv8 | juanrga | 2018/12/23 05:39 AM |
With similar logic nor do frequency (NT) | Megol | 2018/12/23 10:45 AM |
RISC-V inferior to ARMv8 | juanrga | 2018/12/23 05:44 AM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/23 07:21 AM |
RISC-V inferior to ARMv8 | Michael S | 2018/12/20 04:24 PM |
RISC-V inferior to ARMv8 | anon | 2018/12/20 05:22 PM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/21 07:16 PM |
RISC-V inferior to ARMv8 | anon | 2018/12/22 04:53 AM |
Execution runtimes and Spectre | Foo_ | 2018/12/22 07:02 AM |
RISC-V inferior to ARMv8 | Adrian | 2018/12/20 09:51 PM |
RISC-V inferior to ARMv8 | Doug S | 2018/12/21 12:10 AM |
RISC-V inferior to ARMv8 | Adrian | 2018/12/21 12:38 AM |
RISC-V inferior to ARMv8 | Michael S | 2018/12/21 03:31 AM |
RISC-V inferior to ARMv8 | Adrian | 2018/12/21 04:23 AM |
RISC-V inferior to ARMv8 | random person | 2018/12/21 03:04 AM |
RISC-V inferior to ARMv8 | dmcq | 2018/12/21 05:27 AM |
RISC-V inferior to ARMv8 | juanrga | 2018/12/21 11:36 AM |
RISC-V inferior to ARMv8 | Doug S | 2018/12/21 01:02 PM |
RISC-V inferior to ARMv8 | juanrga | 2018/12/21 11:23 AM |
RISC-V inferior to ARMv8 | Adrian | 2018/12/21 12:21 AM |
RISC-V inferior to ARMv8 | anon | 2018/12/21 02:48 AM |
RISC-V inferior to ARMv8 | Adrian | 2018/12/21 04:44 AM |
RISC-V inferior to ARMv8 | anon | 2018/12/21 06:24 AM |
RISC-V inferior to ARMv8 | Adrian | 2018/12/21 05:09 AM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/21 05:28 AM |
RISC-V inferior to ARMv8 | Michael S | 2018/12/21 03:27 AM |
RISC-V inferior to ARMv8 | Gabriele Svelto | 2018/12/21 02:09 PM |
RISC-V inferior to ARMv8 | Maynard Handley | 2018/12/21 03:58 PM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/21 04:43 PM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/21 06:45 PM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/22 05:37 AM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/22 07:54 AM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/22 11:32 AM |
Cracking is not free | Gabriele Svelto | 2018/12/22 03:09 AM |
Cracking is not free | Wilco | 2018/12/22 05:32 AM |
Cracking is not free | Travis Downs | 2018/12/22 08:07 AM |
Cracking is not free | Wilco | 2018/12/22 08:38 AM |
Cracking is not free | Travis Downs | 2018/12/22 08:47 AM |
Cracking is not free | Wilco | 2018/12/22 11:24 AM |
Cracking is not free | Travis Downs | 2018/12/25 04:41 PM |
Cracking is not free | anon.1 | 2018/12/25 09:14 PM |
multi-instruction decode and rename | Paul A. Clayton | 2018/12/22 07:45 PM |
Cracking is not free | Gabriele Svelto | 2018/12/22 01:30 PM |
Cracking is not free | Wilco | 2018/12/23 07:48 AM |
Cracking is not free | Michael S | 2018/12/23 09:09 AM |
Cracking is not free | Gabriele Svelto | 2018/12/26 03:53 PM |
RISC-V inferior to ARMv8 | rwessel | 2018/12/21 02:13 PM |
RISC-V inferior to ARMv8 | Seni | 2018/12/21 03:33 PM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/21 04:33 PM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/21 06:49 PM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/22 05:58 AM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/22 08:03 AM |
RISC-V inferior to ARMv8 | Wilco | 2018/12/22 08:22 AM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/22 08:40 AM |
RISC-V inferior to ARMv8 | dmcq | 2018/12/21 04:57 AM |
RISC-V inferior to ARMv8 | Konrad Schwarz | 2018/12/21 03:25 AM |
RISC-V inferior to ARMv8 | j | 2018/12/21 11:46 AM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/21 07:08 PM |
RISC-V inferior to ARMv8 | dmcq | 2018/12/22 08:45 AM |
RISC-V inferior to ARMv8 | Travis Downs | 2018/12/22 08:50 AM |
RISC-V inferior to ARMv8 | Michael S | 2018/12/22 09:15 AM |
RISC-V inferior to ARMv8 | dmcq | 2018/12/22 11:41 AM |
RISC-V inferior to ARMv8 | AnonQ | 2018/12/22 09:13 AM |
RISC-V gut feelings | dmcq | 2018/12/20 08:41 AM |
RISC-V initial take | Konrad Schwarz | 2018/12/21 03:17 AM |
RISC-V initial take | dmcq | 2018/12/21 04:23 AM |
RISC-V gut feelings | Montaray Jack | 2018/12/22 03:56 PM |
RISC-V gut feelings | dmcq | 2018/12/23 05:38 AM |
RISC-V Summit Proceedings | juanrga | 2018/12/21 11:47 AM |
RISC-V Summit Proceedings | dmcq | 2018/12/22 07:21 AM |
RISC-V Summit Proceedings | Montaray Jack | 2018/12/22 03:03 PM |
RISC-V Summit Proceedings | dmcq | 2018/12/23 05:39 AM |
RISC-V Summit Proceedings | anon2 | 2018/12/21 11:57 AM |
RISC-V Summit Proceedings | Michael S | 2018/12/22 09:36 AM |
RISC-V Summit Proceedings | Anon | 2018/12/22 06:51 PM |
Not Stanford MIPS but commercial MIPS | Paul A. Clayton | 2018/12/23 04:05 AM |
Not Stanford MIPS but commercial MIPS | Michael S | 2018/12/23 04:49 AM |
Not Stanford MIPS but commercial MIPS | dmcq | 2018/12/23 05:52 AM |