Michael S (already5chosen.delete@this.yahoo.com) on December 22, 2018 8:36 am wrote:
[snip[
> I am not sure how lucid he still is.
> Couple of years ago he said that RISC-V is a direct successor of Berkeley RISC tradition,
> when in fact anybody an see that RISV-V is a very close derivative of Stanford MIPS and
> has as little in common with earlier Berkeley RISCs as two RISC ISA possible can.

Stanford MIPS was a bit odd in having two "micro-ops" per instruction (which also limited it to 16 GRPS, if I recall correctly). The differences between RISC-V and Berkeley RISC (that are not also differences from commercial MIPS, i.e., delayed branches, fixed length encoding, etc.) seem to be GPR vs.condition code and register windows. (There may be some other significant differences. I do not know if Berkeley RISC shared the strange encoding choices of SPARC such as full 32-bit immediate addressed calls or if it also had "CISCy" CAS vs. ll/sc.)

Stanford MIPS (if I recall correctly) also had the neat-ish feature of folding the ASID into the address space to allow more small address spaces or fewer large address spaces.

I agree that the "feel" of RISC-V is more like that of commercial MIPS (streamlined), but RISC-V avoids special casing multiplication/division and the use of load/store high and load/store low for handling unaligned loads. (This might be a difference between instruction complexity definition of RISC (Stanford?) vs. instruction count definition of RISC (Berkeley).)