Definitely a mistake

By: carop (carop.delete@this.inlimbo.net), December 22, 2018 8:09 pm
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on December 22, 2018 7:45 am wrote:

>
> The very next sentence: "Until recently, eDRAM was considered to be too slow for this use.
> However, a breakthrough in technology made by IBM has eliminated that limitation."
>
> Also on p.91: "L1 and L2 caches use eDRAM, and are private for each PU core".
>

The following paper on physical design of z14 has a section on High-performance SRAM array design in 14nm FinFET technology:

https://ieeexplore.ieee.org/document/8276273

Replacing dual power supplies with a single power supply: In 22nm and earlier technology nodes, zServer arrays used dual power supplies (VDD and VCS), where VCS was a dedicated SRAM supply while VDD was for general logic [24]. This dual-voltage setup enables the higher voltage to support improved read/write margins and responses for the higher-VT SRAM cells, without impacting the main logic voltage and associated power consumption. VCS was typically set ~0.15 V higher than VDD to improve array functionality and performance at the cost of additional power routing complexities and verification challenges. In 22nm, VDD and VCS were set to 1.15 V and 1.3 V, respectively. In 14nm, our Vmax was scaled to 1.1 V, which unfortunately constrained the VCS-VDD voltage differential to far less than 0.15 V and rendered the dual power supply strategy ineffective; therefore, a single supply strategy (VDD only) was adopted for z14 array designs.


Partial-swing global bit line structure: In high performance core SRAM design, the bit column circuitry typically consumes 40% to 50% of the macro’s total power dissipation. With a hierarchical bit line structure, much of this is consumed by global bit line switching power. To lower the bit column power, a bit-select-localeval (LBSEL) [11] was used in conjunction with a partial-swing global bit line circuit. Figure 7 shows the schematic of this bit circuit topology, specifically a 128-word line (WL) by 2-bit line (BL) hierarchical column read operation.








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IBM Going with Samsung after dumping GlobalFoundriesAnon2018/12/20 12:07 PM
  IBM Going with Samsung after dumping GlobalFoundriesitsmydamnation2018/12/20 03:02 PM
    IBM Going with Samsung after dumping GlobalFoundriesanon2018/12/20 04:50 PM
    IBM Going with Samsung after dumping GlobalFoundriesMaynard Handley2018/12/20 07:43 PM
      IBM Going with Samsung after dumping GlobalFoundriesMichael S2018/12/21 04:46 AM
        IBM Going with Samsung after dumping GlobalFoundriesanon2018/12/21 06:30 AM
          IBM Going with Samsung after dumping GlobalFoundriesMichael S2018/12/21 07:39 AM
            IBM Going with Samsung after dumping GlobalFoundriesanon2018/12/21 08:24 AM
            Definitely a mistakeDavid Kanter2018/12/21 09:09 AM
              Definitely a mistakeMichael S2018/12/22 08:45 AM
                Definitely a mistakedmcq2018/12/22 11:26 AM
                Definitely a mistakeRobert Williams2018/12/22 11:40 AM
                Definitely a mistakesomeone2018/12/22 01:46 PM
                L1 caches are SRAMDavid Kanter2018/12/22 02:27 PM
                Definitely a mistakeanon2018/12/22 02:30 PM
                Definitely a mistakecarop2018/12/22 08:09 PM
                L1 caches are SRAMjuanrga2018/12/23 05:23 AM
    IBM Going with Samsung after dumping GlobalFoundriesDavid Kanter2018/12/20 09:28 PM
      IBM Going with Samsung after dumping GlobalFoundriesKevin G2018/12/21 08:57 AM
        Samsung fabbed Alpha 21164A chips in 1996/7Mark Roulo2018/12/21 05:24 PM
          Samsung fabbed Alpha 21164A chips in 1996/7Kevin G2018/12/25 03:03 PM
      IBM Going with Samsung after dumping GlobalFoundriesAdrian2018/12/21 11:55 PM
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