Zen PHY speeds

By: Jeff S. (fakity.delete@this.fake.com), January 14, 2019 12:40 pm
Room: Moderated Discussions
Ricardo B (ricardo.b.delete@this.xxxxx.xx) on January 14, 2019 11:06 am wrote:
> Adrian (a.delete@this.acm.org) on January 13, 2019 8:51 pm wrote:
> >
> > 2. The new I/O dies also need higher speed SERDES for the other interfaces, e.g. for
> > the inter-chip links, probably up to at least 20 Gb/s, more likely up to 25 Gb/s.
> >
> > Such SERDES designs were already existing and proven for the IBM process, while the original
> > Zen 14 nm process seemed to not be able to reach serial speeds much above 10 Gb/s.
> I double GloFo 14 nm process is a limiting factor for SERDES speed.
> Here, a 28 Gbit/s SERDES implemented in TSMC 28 nm.
> https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6894632

The Zeppelin PHYs were rated for 12 Gbps IIRC, and the Zen 2 IO die PHYs will need to rate close to 17 Gbps for the PCIe 4.0. The next realistic step up is 28 Gbps for 25/50/100 GbE, but there is no reason to expect that on the AM4 platform, and not very likely on Epyc either IMO.

I could imagine AMD putting faster IFOP/GMI links on Zen 2 (Peak core bandwidth is doubling with 2*256b AVX and the new 2*32B L1D load datapath, and fatter L2-L3-DDR links would help some workloads a lot.), but a lot of this will depend on how much of Zen 2 IF AMD keeps synchronously clocked with DRAM.

My guess is that Ryzen 3's PCIe 4.0 PHYs will be substantially beefier, the DDR4 controller will be marginally larger and higher performance, and the IFOP will be not be much if any higher clocked, but potentially widened. It is arguable that Zen 2 will need a faster/wider IF to cope with doubled per-code AVX throuhput (only L1D datapath width doubling has been confirmed so far), and more lanes is generally kinder on the power budget than higher clocks. Moreover, compute chiplets should only need 1 IFOP port instead of 4 now (and AM4 IO dies only 2?), so spending a bit of floorplan there is not too extravagant. Also, compute chiplet die has a lot of perimeter space no longer being used by PCIe, DDR, and USB lanes, so lane density concerns there are drastically diminished.
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