eDRAM too expensive

By: Maynard Handley (name99.delete@this.name99.org), January 14, 2019 2:43 pm
Room: Moderated Discussions
anon (spam.delete.delete.delete@this.this.this.spam.com) on January 14, 2019 1:00 pm wrote:
> Maynard Handley (name99.delete@this.name99.org) on January 14, 2019 10:38 am wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on January 13, 2019 2:34 pm wrote:
> > > anon³ (alt-0179.delete@this.test.example.test) on January 13, 2019 1:17 pm wrote:
> > > > JS (null.delete@this.null.com) on January 12, 2019 1:05 am wrote:
> > > > > > We could wait a little about power consumption.
> > > > > > The node shift is unable to halve the power consumption
> > > > > > on an high power cpu, moreover half the SKU is on 14nm.
> > > > > > More likely AMD demoed on a very light development motherboard unable of overclock. My bet
> > > > > > Intel was on a power hungry plataform thinked to allow more than 300W under overclocking.
> > > > > >
> > > > > > Better wait real products.
> > > > > > For now is only smart marketing.
> > > > >
> > > > > Correct me if I'm wrong but the IO die on 14nm shouldn't be a significant limiting factor
> > > > > for the chip. It's relative simplicity to the processor die should make it clock relatively
> > > > > well, or at least parallel silicon could be added to make up for any deficit?
> > > >
> > > > IO die on GF/IBM 14nm is going to be just fine. IO structures scale abysmally with
> > > > process (it's all about gate oxides and voltage rating), so once you've paid the
> > > > costs to go off-die, it doesn't matter much what process the IO die is on.
> > > >
> > > > It's interesting that the IO die is claimed to be "14nm", though, not "12nm". Zen+
> > > > is 12nm, so there's no reason the IO die wouldn't also be on 12nm. At least, that's
> > > > if the target process was GF 14LP/12LP (which are almost the same process).
> > > >
> > > > That implies the target is actually GF/IBM's 14HP. And that lines up perfectly, since by all accounts
> > > > 14HP is an excellent choice for IO-heavy designs. It also implies that there could be eDRAM on the IO
> > > > die, but that seems unlikely given the target die size and yields. Perhaps they've managed some clever
> > > > use of a small amount of eDRAM somewhere (it does seem the sort of thing that would be useful on an
> > > > all-IO die), or perhaps they've got a custom eDRAM-less process variant to save a bit of cost.
> > >
> > > eDRAM is incredibly expensive and SRAM is better for small
> > > arrays. I wouldn't worry too much about what they call it.
> >
> > What does a statement like this ("eDRAM is incredibly expensive") actually mean, David?
> > I'm not being sarcastic here, there's a genuine disconnect between what
> > you're saying and the way I would have conceptualized the issue.
> >
> > One initial possibility might be on the IP/design side, that the IP required or design/verify
> > man-hours are large compared to SRAM or logic. This seems unlikely, but of course maybe
> > IBM is the only one who knows how to do it and they don't want to share?
> >
> > A second possibility would be the manufacturing, but again I don't really see how. Once you're
> > down at the level of masks and processes, isn't the price basically driven by how many iterations
> > are required of how much area? eDRAM doesn't, as far as I know, require uniquely expensive
> > chemical reagents, or uniquely expensive machinery, or more masks than usual.
> >
> > A third possibility is that yield is substantially lower. This is certainly possible in principle,
> > but if course normal DRAMs get made in huge volumes. Of course normal DRAMs happen in a specialized
> > fab... So if I had to guess (and if the statement is true) this is where my money would be.
> >
> > A fourth possibility is that testing (or characterization, somehow required for
> > functioning) is a lot more expensive than for SRAMs, but again I can't see how.
> >
> > One issue is what is meant by "incredibly expensive"? If we're talking say 10% higher cost than SRAMs
> > (which is not what I would call "incredible"), any of these possibilities might be relevant. But
> > if we're talking 2x, 3x or more, the only option I can see forcing that is terrible yields.
> >
> > If there is NOT a sea of storage (huge L4 of SRAM or eDRAM, but to me, apart from the economics,
> > eDRAM seems a better choice) it's hard to see why that 14nm die is quite as large as it is.
> >
> > There is a longer term issue for how this plays out. To *me* the correct answer for everyone (from Apple to
> > AMD to Intel) going forward is an IO die incorporating memory controller, and huge L4 (sans tags), with the
> > logic sitting on top of that so that communication is via
> > bumps or TSVs, high bandwidth low latency low power,
> > and with L4 tags on the logic die. L4 could be SRAM, eDRAM,
> > or MRAM depending on what tech gives the best balance
> > of power vs latency vs capacity. So the primary interesting issue is how soon we get to that...
> >
> >
>
> It's not about "10% higher cost than SRAMs" because eDRAM is denser. It simply adds layers and steps that are
> only needed for eDRAM and increase the cost of the whole wafer. If your die would've been 80% SRAM then the
> smaller dies with eDRAM might very well be cheaper. But saving 5 mm² on a 100+ mm² die is a net loss.

This is not answering the question, it's simply repeating what David said, in a louder voice.

HOW MANY ADDITIONAL LAYERS and STEPS?
HOW MUCH more expensive?
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
AMD CESsomeguy2019/01/10 02:06 PM
  AMD CESJeff S.2019/01/10 02:53 PM
    AMD CESDomaldel2019/01/11 06:37 PM
      AMD CESnoone2019/01/11 10:05 PM
        AMD CESDomaldel2019/01/12 01:20 AM
          AMD CESarifureta2019/01/12 07:09 AM
            AMD CESDomaldel2019/01/13 01:57 AM
              AMD CESMontaray Jack2019/01/17 10:00 AM
                AMD CESMontaray Jack2019/01/17 12:32 PM
  AMD CEShobold2019/01/10 03:17 PM
    AMD CESJan Olšan2019/01/10 03:30 PM
    AMD CESAdrian2019/01/10 09:37 PM
      AMD CESAlberto2019/01/11 11:13 AM
        AMD CESJS2019/01/12 02:05 AM
          AMD IO dieanon³2019/01/13 02:17 PM
            AMD IO dieanon2019/01/13 03:26 PM
            eDRAM too expensiveDavid Kanter2019/01/13 03:34 PM
              eDRAM too expensiveAdrian2019/01/13 09:51 PM
                eDRAM too expensiveAdrian2019/01/13 10:01 PM
                eDRAM too expensiveRicardo B2019/01/14 12:06 PM
                  Zen PHY speedsJeff S.2019/01/14 12:40 PM
                  eDRAM too expensiveAdrian2019/01/14 01:44 PM
                    Zen target process (was: eDRAM too expensive)hobold2019/01/14 03:42 PM
                      Zen target process (was: eDRAM too expensive)Adrian2019/01/14 10:13 PM
                        Zen target process (was: eDRAM too expensive)hobold2019/01/15 09:28 PM
                    eDRAM too expensiveRicardo B2019/01/15 04:40 AM
                    eDRAM too expensiveRicardo B2019/01/15 09:26 AM
              eDRAM too expensiveMaynard Handley2019/01/14 11:38 AM
                eDRAM too expensiveanon2019/01/14 02:00 PM
                  eDRAM too expensiveMaynard Handley2019/01/14 02:43 PM
                    eDRAM too expensiveDan Fay2019/01/14 03:16 PM
                      eDRAM too expensiveMaynard Handley2019/01/14 04:40 PM
                        eDRAM too expensiveDan Fay2019/01/14 05:58 PM
                    eDRAM too expensivesomeone2019/01/15 09:20 AM
                eDRAM too expensiveanon2019/01/14 04:34 PM
                  eDRAM too expensiveMaynard Handley2019/01/14 06:34 PM
                eDRAM too expensiveanon2019/01/15 02:06 AM
            AMD IO diejuanrga2019/01/14 04:04 AM
              AMD IO dieMaynard Handley2019/01/14 11:42 AM
                AMD IO dieAlberto2019/01/14 03:00 PM
                AMD IO diejuanrga2019/01/15 03:54 AM
                AMD IO die size & functionalityWes Felter2019/01/15 12:12 PM
                  AMD IO die size & functionalityjuanrga2019/01/15 12:43 PM
                  AMD IO die size & functionalityAlberto2019/01/15 01:57 PM
                    AMD CPU die size & functionalityWes Felter2019/01/15 05:35 PM
                      AMD CPU die size & functionalityanon2019/01/16 02:32 AM
                        AMD CPU die size & functionalityAlberto2019/01/16 06:40 AM
                      AMD CPU die size & functionalityJan Olšan2019/01/16 08:11 AM
                  AMD IO die size & functionalityMaynard Handley2019/01/16 10:17 AM
Reply to this Topic
Name:
Email:
Topic:
Body: No Text
How do you spell green?