By: hobold (hobold.delete@this.vectorizer.org), January 14, 2019 2:42 pm
Room: Moderated Discussions
Adrian (a.delete@this.acm.org) on January 14, 2019 12:44 pm wrote:
[...]
> I doubt that
> the first Zen generation was very far from an optimal design.
>
There is a repeated claim made a few times by top AMD management folks that the Zen project was aimed from the start to compete with a few successive generations on intel's roadmap.
Assuming that AMD is a very resource limited company these days, how realistic would it be for them to try and save manpower by designing a 7nm chip, but with just enough compromises to be able to implement it on 14nm without it being totally crippled?
In other words, Zen seeming to be wire limited at 14nm, could this be a side effect of the chip being balanced for a different relation between wire delays and transistor delays? More targeted at what 7nm is expected to be rather than what 14nm actually is?
I am not even speculating here. Just wondering if A), in a situation where we are thermally limited anyway, could we tolerate wires being 10% to 15% too slow (compared to some optimal balance point of transistor speed)?
And B), would doing so actually reduce the amount of design work by a significant enough amount? I.e. is it even possible to design circuits for re-use at a finer process node (if you are willing to accept compromises at the coarser node)?
[...]
> I doubt that
> the first Zen generation was very far from an optimal design.
>
There is a repeated claim made a few times by top AMD management folks that the Zen project was aimed from the start to compete with a few successive generations on intel's roadmap.
Assuming that AMD is a very resource limited company these days, how realistic would it be for them to try and save manpower by designing a 7nm chip, but with just enough compromises to be able to implement it on 14nm without it being totally crippled?
In other words, Zen seeming to be wire limited at 14nm, could this be a side effect of the chip being balanced for a different relation between wire delays and transistor delays? More targeted at what 7nm is expected to be rather than what 14nm actually is?
I am not even speculating here. Just wondering if A), in a situation where we are thermally limited anyway, could we tolerate wires being 10% to 15% too slow (compared to some optimal balance point of transistor speed)?
And B), would doing so actually reduce the amount of design work by a significant enough amount? I.e. is it even possible to design circuits for re-use at a finer process node (if you are willing to accept compromises at the coarser node)?
| Topic | Posted By | Date |
|---|---|---|
| AMD CES | someguy | 2019/01/10 01:06 PM |
| AMD CES | Jeff S. | 2019/01/10 01:53 PM |
| AMD CES | Domaldel | 2019/01/11 05:37 PM |
| AMD CES | noone | 2019/01/11 09:05 PM |
| AMD CES | Domaldel | 2019/01/12 12:20 AM |
| AMD CES | arifureta | 2019/01/12 06:09 AM |
| AMD CES | Domaldel | 2019/01/13 12:57 AM |
| AMD CES | Montaray Jack | 2019/01/17 09:00 AM |
| AMD CES | Montaray Jack | 2019/01/17 11:32 AM |
| AMD CES | hobold | 2019/01/10 02:17 PM |
| AMD CES | Jan Olšan | 2019/01/10 02:30 PM |
| AMD CES | Adrian | 2019/01/10 08:37 PM |
| AMD CES | Alberto | 2019/01/11 10:13 AM |
| AMD CES | JS | 2019/01/12 01:05 AM |
| AMD IO die | anon³ | 2019/01/13 01:17 PM |
| AMD IO die | anon | 2019/01/13 02:26 PM |
| eDRAM too expensive | David Kanter | 2019/01/13 02:34 PM |
| eDRAM too expensive | Adrian | 2019/01/13 08:51 PM |
| eDRAM too expensive | Adrian | 2019/01/13 09:01 PM |
| eDRAM too expensive | Ricardo B | 2019/01/14 11:06 AM |
| Zen PHY speeds | Jeff S. | 2019/01/14 11:40 AM |
| eDRAM too expensive | Adrian | 2019/01/14 12:44 PM |
| Zen target process (was: eDRAM too expensive) | hobold | 2019/01/14 02:42 PM |
| Zen target process (was: eDRAM too expensive) | Adrian | 2019/01/14 09:13 PM |
| Zen target process (was: eDRAM too expensive) | hobold | 2019/01/15 08:28 PM |
| eDRAM too expensive | Ricardo B | 2019/01/15 03:40 AM |
| eDRAM too expensive | Ricardo B | 2019/01/15 08:26 AM |
| eDRAM too expensive | Maynard Handley | 2019/01/14 10:38 AM |
| eDRAM too expensive | anon | 2019/01/14 01:00 PM |
| eDRAM too expensive | Maynard Handley | 2019/01/14 01:43 PM |
| eDRAM too expensive | Dan Fay | 2019/01/14 02:16 PM |
| eDRAM too expensive | Maynard Handley | 2019/01/14 03:40 PM |
| eDRAM too expensive | Dan Fay | 2019/01/14 04:58 PM |
| eDRAM too expensive | someone | 2019/01/15 08:20 AM |
| eDRAM too expensive | anon | 2019/01/14 03:34 PM |
| eDRAM too expensive | Maynard Handley | 2019/01/14 05:34 PM |
| eDRAM too expensive | anon | 2019/01/15 01:06 AM |
| AMD IO die | juanrga | 2019/01/14 03:04 AM |
| AMD IO die | Maynard Handley | 2019/01/14 10:42 AM |
| AMD IO die | Alberto | 2019/01/14 02:00 PM |
| AMD IO die | juanrga | 2019/01/15 02:54 AM |
| AMD IO die size & functionality | Wes Felter | 2019/01/15 11:12 AM |
| AMD IO die size & functionality | juanrga | 2019/01/15 11:43 AM |
| AMD IO die size & functionality | Alberto | 2019/01/15 12:57 PM |
| AMD CPU die size & functionality | Wes Felter | 2019/01/15 04:35 PM |
| AMD CPU die size & functionality | anon | 2019/01/16 01:32 AM |
| AMD CPU die size & functionality | Alberto | 2019/01/16 05:40 AM |
| AMD CPU die size & functionality | Jan Olšan | 2019/01/16 07:11 AM |
| AMD IO die size & functionality | Maynard Handley | 2019/01/16 09:17 AM |
