By: anon (anon.delete@this.anonb.com), January 14, 2019 3:34 pm
Room: Moderated Discussions
Maynard Handley (name99.delete@this.name99.org) on January 14, 2019 10:38 am wrote:
>
> A third possibility is that yield is substantially lower. This is certainly possible in principle,
> but if course normal DRAMs get made in huge volumes. Of course normal DRAMs happen in a specialized
> fab... So if I had to guess (and if the statement is true) this is where my money would be.
Note that IBM eDRAM is physically a very different device from normal DRAM. In normal DRAM, the capacitor is built above the silicon substrate. In IBM eDRAM, the capacitors are dug deep into the substrate.
The reason for this is that having the capacitor arrays above the transistors means that you need to have very long vias connecting the surface of the chip to the transistors. Since the caps also need to be close to the transistors, this limits your metal stack to just a few useful layers close to the transistors, and then the rest very far away. This is sort of completely incompatible with any sort of properly high-speed logic.
In comparison, the IBM eDRAM is basically non-intrusive to a normal logic chip -- you can build all the things you could otherwise, and just dig holes for eDRAM where you want them. The cost is that yield is terrible compared to normal DRAM, and you need special processing steps.
>
> A third possibility is that yield is substantially lower. This is certainly possible in principle,
> but if course normal DRAMs get made in huge volumes. Of course normal DRAMs happen in a specialized
> fab... So if I had to guess (and if the statement is true) this is where my money would be.
Note that IBM eDRAM is physically a very different device from normal DRAM. In normal DRAM, the capacitor is built above the silicon substrate. In IBM eDRAM, the capacitors are dug deep into the substrate.
The reason for this is that having the capacitor arrays above the transistors means that you need to have very long vias connecting the surface of the chip to the transistors. Since the caps also need to be close to the transistors, this limits your metal stack to just a few useful layers close to the transistors, and then the rest very far away. This is sort of completely incompatible with any sort of properly high-speed logic.
In comparison, the IBM eDRAM is basically non-intrusive to a normal logic chip -- you can build all the things you could otherwise, and just dig holes for eDRAM where you want them. The cost is that yield is terrible compared to normal DRAM, and you need special processing steps.
Topic | Posted By | Date |
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