eDRAM too expensive

By: Dan Fay (daniel.fay.delete@this.gmail.com), January 14, 2019 4:58 pm
Room: Moderated Discussions
Maynard Handley (name99.delete@this.name99.org) on January 14, 2019 3:40 pm wrote:
> Dan Fay (daniel.fay.delete@this.gmail.com) on January 14, 2019 2:16 pm wrote:
> > Maynard Handley (name99.delete@this.name99.org) on January 14, 201
> > > > It's not about "10% higher cost than SRAMs" because eDRAM
> > > > is denser. It simply adds layers and steps that are
> > > > only needed for eDRAM and increase the cost of the whole wafer. If your die would've been 80% SRAM then the
> > > > smaller dies with eDRAM might very well be cheaper. But saving 5 mm² on a 100+ mm² die is a net loss.
> > >
> > > This is not answering the question, it's simply repeating what David said, in a louder voice.
> > >
> > > HOW MANY ADDITIONAL LAYERS and STEPS?
> > > HOW MUCH more expensive?
> >
> > This is a *really* old article, but IBM estimates here ~20% more:
> >
> > https://www.edn.com/electronics-news/4336936/IBM-Pushes-eDRAM-as-SRAM-Replacement
> >
> > They claim here 3 more masks. I don't know if they're "critical layers"
> > though. If they are, you might have to double or quadruple that number.
> >
> >
>
> But that's kinda my point. Articles like that refer to a reality so different from today that it's
> impossible (IMHO) to generalize from them. If all it takes is still (and who knows whether this
> is even CLOSE to true) is three extra masks and a few extra steps, to create the deep trench, what
> could have been 20% extra costs (not what I would have called "incredibly expensive" even then)
> might be lost in the noise of today's almost 100 masks and almost one thousand steps.
>
> I don't want to harp on the "incredibly expensive" because I'm a dick (though perhaps I am...) but
> because all too often people make wild claims about cost that are just not that important when looked
> at closely. A 20% higher cost IS higher, yes, and it matters if you're selling into a commodity market
> that is buying based on price. But it's NOT a big deal if you're selling into a market that is buying
> based on something other than price, or packaged into something much larger.
> Apple doesn't REALLY care if they can add 20% in cost to the A13, but thereby acquire
> some sort of unique (or at least impressive) advantage for iPhones, whether it's new functionality
> (better computational photography than Pixel?) or much better battery life. And $10 more
> in the cost of an A13 can be lost in the overall cost of an iPhone.
>
> As for AMD, well, that depends on the extent to which they can deliver (and market) a singular
> product. IF they could use a huge L4 either to get better-than-Intel-level energy in mobile,
> or better-than-Intel-level single threaded performance, they could charge Intel-level prices.
> It's clearly harder for them than for Apple; so everything depends on the precise numbers ---
> how much does cost go up, how much does performance go up, how much does energy go down.
>
> My guess is it IS overall a win, even for AMD's space. But it DOES require a redesign
> of the system, not just the sort of minor tweak that this year's product appears
> to be (ie a tock - new micro-arch, rather than a tick - new process).

I found this article, which might suggest why IBM is the only one doing high-performance CPUs with on-die eDRAM: https://www.src.org/calendar/e003676/barth.pdf

Some key facts:
1. It's 3x as dense as SRAM
2. SOI-based eDRAM is half as expensive as bulk eDRAM
3. The SOI-based deep trench architecture allows for fabricating the capacitors first. (ASIDE: ISTR that other eDRAM technologies fabricate the cap last using some very high temperature processing. These high temperatures in turn degrade the performance of the logic transistors).

So given 1-3, to do high-performance, on-die eDRAM, you need:
1. Designs employing a lot of high-performance, on-die memory to justify the density benefit to the point where it outweighs the added wafer processing costs. Given the higher wafer fab costs and limited amount of DRAM you can integrate on die (you can't do 1GB+ of eDRAM), the only big use for high-performance, on-die eDRAM is for large caches.
2. SOI. While the cost savings are significant, there's also the issue of degrading the logic transistors if you don't use a deep trench capacitor, so you need deep trench capacitors, which apparently requires SOI. For high-performance designs, everyone seems to have given up on SOI except for IBM.

So in the end, you have to develop a special process using special wafers (that I think are only made by one company, Soitec) for a single use case (high-end microprocessors with large, on-die caches). Moreover, this special process needs to be integrated into bleeding-edge processes, increasing your schedule risk.

The fact that there's only one company on Earth (IBM, now GlobalFoundries) that actually provides a state-of-the-art process with on-die eDRAM capability suggests that the business case for on-die eDRAM is too narrow to justify the NRE.

*TSMC and others (including UMC) offer eDRAM on older processes (40nm and earlier). I suspect these are mainly used where a) bleeding-edge performance isn't necessary; and b) to eliminate the need for external DRAMs in some embedded devices.

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              eDRAM too expensiveMaynard Handley2019/01/14 10:38 AM
                eDRAM too expensiveanon2019/01/14 01:00 PM
                  eDRAM too expensiveMaynard Handley2019/01/14 01:43 PM
                    eDRAM too expensiveDan Fay2019/01/14 02:16 PM
                      eDRAM too expensiveMaynard Handley2019/01/14 03:40 PM
                        eDRAM too expensiveDan Fay2019/01/14 04:58 PM
                    eDRAM too expensivesomeone2019/01/15 08:20 AM
                eDRAM too expensiveanon2019/01/14 03:34 PM
                  eDRAM too expensiveMaynard Handley2019/01/14 05:34 PM
                eDRAM too expensiveanon2019/01/15 01:06 AM
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                        AMD CPU die size & functionalityAlberto2019/01/16 05:40 AM
                      AMD CPU die size & functionalityJan Olšan2019/01/16 07:11 AM
                  AMD IO die size & functionalityMaynard Handley2019/01/16 09:17 AM
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