Zen target process (was: eDRAM too expensive)

By: Adrian (a.delete@this.acm.org), January 14, 2019 9:13 pm
Room: Moderated Discussions
hobold (hobold.delete@this.vectorizer.org) on January 14, 2019 2:42 pm wrote:
>
> There is a repeated claim made a few times by top AMD management folks that the Zen project
> was aimed from the start to compete with a few successive generations on intel's roadmap.
>
> Assuming that AMD is a very resource limited company these days, how realistic would
> it be for them to try and save manpower by designing a 7nm chip, but with just enough
> compromises to be able to implement it on 14nm without it being totally crippled?
>
> In other words, Zen seeming to be wire limited at 14nm, could this be a side effect of
> the chip being balanced for a different relation between wire delays and transistor delays?
> More targeted at what 7nm is expected to be rather than what 14nm actually is?
>


This would have been a wise strategy, but it is very difficult to implement it, so I do not believe it to be very likely, at least not in the detailed design of the blocks or cells which compose the design.

At a higher level of abstraction they certainly must have thought about a roadmap of evolution of various blocks, e.g. that they will use 128-bit ALUs at 14 nm and 256-bit ALUs at 7 nm and that they will have a certain amount of bandwidth for interconnecting the chiplets at each available process and that various internal structures, register sets and caches will have certain sizes at each generation.


At the detailed design however, it would have been difficult to do anything to make easier the design for future processes.

The chip design is iterative, after an initial design of the higher-level logic behavior & structure and of the various blocks and components is done, the process-specific libraries of models are used and the design is simulated many times,

After many improvements are done, the layout is done, then using process-specific data the delays & parasitic components are extracted from the layout and back-annotated to the schematic.

The simulations are repeated, now with different results. The schematic is now tweaked, either with simple changes like modifying transistor sizes, but also totally different blocks and cells could be selected to implement certain parts after seeing the simulation results. After many simulations and changes, the layout is redone. Then the delays and the parasitics are extracted again and the design process is repeated.


In order to tune the design for the next process, you would have to use for simulations 2 sets of model libraries, for the current process and for the future process and also you would have to use 2 versions of the extraction tools. This would double the number of simulations and you would have to find a compromise between the simulation results for the 2 processes.

This would be too much work and the simulation for the future process could not be accurate anyway, because the future process might have a different number of types of transistors, so just replacing the models in the current schematic would not be a good prediction of the performance of the future process. Also, the future process will have a different number and type of layers, so the estimation of the extracted values for the future process based on the current layout will also be very inaccurate.



In conclusion, I do not believe that such a strategy can be applied to the detailed design, e.g. to the design of a SERDES or of an ALU.


On the other hand, it is certainly possible to have a certain number of rules of thumb, e.g. predicted values for the sizes of the logic cells and of the bit-cells for memories and registers at each process generation, predicted values for the power consumption at various clock frequencies of ALUs, buffers, serializers and so on.

Using such approximate rules, it should be possible to have a strategy of evolution of the CPU structure at each process generation and it should be possible indeed to choose an architecture that will be closer to optimal at a future process node, in order to mimimize the design effort.














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                eDRAM too expensiveRicardo B2019/01/14 11:06 AM
                  Zen PHY speedsJeff S.2019/01/14 11:40 AM
                  eDRAM too expensiveAdrian2019/01/14 12:44 PM
                    Zen target process (was: eDRAM too expensive)hobold2019/01/14 02:42 PM
                      Zen target process (was: eDRAM too expensive)Adrian2019/01/14 09:13 PM
                        Zen target process (was: eDRAM too expensive)hobold2019/01/15 08:28 PM
                    eDRAM too expensiveRicardo B2019/01/15 03:40 AM
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              eDRAM too expensiveMaynard Handley2019/01/14 10:38 AM
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                eDRAM too expensiveanon2019/01/14 03:34 PM
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