eDRAM too expensive

By: anon (spam.delete.delete.delete@this.this.this.spam.com), January 15, 2019 1:06 am
Room: Moderated Discussions
Maynard Handley (name99.delete@this.name99.org) on January 14, 2019 10:38 am wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on January 13, 2019 2:34 pm wrote:
> > anon³ (alt-0179.delete@this.test.example.test) on January 13, 2019 1:17 pm wrote:
> > > JS (null.delete@this.null.com) on January 12, 2019 1:05 am wrote:
> > > > > We could wait a little about power consumption.
> > > > > The node shift is unable to halve the power consumption
> > > > > on an high power cpu, moreover half the SKU is on 14nm.
> > > > > More likely AMD demoed on a very light development motherboard unable of overclock. My bet
> > > > > Intel was on a power hungry plataform thinked to allow more than 300W under overclocking.
> > > > >
> > > > > Better wait real products.
> > > > > For now is only smart marketing.
> > > >
> > > > Correct me if I'm wrong but the IO die on 14nm shouldn't be a significant limiting factor
> > > > for the chip. It's relative simplicity to the processor die should make it clock relatively
> > > > well, or at least parallel silicon could be added to make up for any deficit?
> > >
> > > IO die on GF/IBM 14nm is going to be just fine. IO structures scale abysmally with
> > > process (it's all about gate oxides and voltage rating), so once you've paid the
> > > costs to go off-die, it doesn't matter much what process the IO die is on.
> > >
> > > It's interesting that the IO die is claimed to be "14nm", though, not "12nm". Zen+
> > > is 12nm, so there's no reason the IO die wouldn't also be on 12nm. At least, that's
> > > if the target process was GF 14LP/12LP (which are almost the same process).
> > >
> > > That implies the target is actually GF/IBM's 14HP. And that lines up perfectly, since by all accounts
> > > 14HP is an excellent choice for IO-heavy designs. It also implies that there could be eDRAM on the IO
> > > die, but that seems unlikely given the target die size and yields. Perhaps they've managed some clever
> > > use of a small amount of eDRAM somewhere (it does seem the sort of thing that would be useful on an
> > > all-IO die), or perhaps they've got a custom eDRAM-less process variant to save a bit of cost.
> >
> > eDRAM is incredibly expensive and SRAM is better for small
> > arrays. I wouldn't worry too much about what they call it.
>
> What does a statement like this ("eDRAM is incredibly expensive") actually mean, David?
> I'm not being sarcastic here, there's a genuine disconnect between what
> you're saying and the way I would have conceptualized the issue.
>
> One initial possibility might be on the IP/design side, that the IP required or design/verify
> man-hours are large compared to SRAM or logic. This seems unlikely, but of course maybe
> IBM is the only one who knows how to do it and they don't want to share?
>
> A second possibility would be the manufacturing, but again I don't really see how. Once you're
> down at the level of masks and processes, isn't the price basically driven by how many iterations
> are required of how much area? eDRAM doesn't, as far as I know, require uniquely expensive
> chemical reagents, or uniquely expensive machinery, or more masks than usual.
>
> A third possibility is that yield is substantially lower. This is certainly possible in principle,
> but if course normal DRAMs get made in huge volumes. Of course normal DRAMs happen in a specialized
> fab... So if I had to guess (and if the statement is true) this is where my money would be.
>
> A fourth possibility is that testing (or characterization, somehow required for
> functioning) is a lot more expensive than for SRAMs, but again I can't see how.
>
> One issue is what is meant by "incredibly expensive"? If we're talking say 10% higher cost than SRAMs
> (which is not what I would call "incredible"), any of these possibilities might be relevant. But
> if we're talking 2x, 3x or more, the only option I can see forcing that is terrible yields.
>
> If there is NOT a sea of storage (huge L4 of SRAM or eDRAM, but to me, apart from the economics,
> eDRAM seems a better choice) it's hard to see why that 14nm die is quite as large as it is.
>

To clarify that: Summit Ridge is 213 mm², of that only 2x44 mm² are the CCX. Of course some of the rest will be on the 8 core chiplets, but PCIe 4.0 and so on will take up more space so I don't see any reason why and how they'd put a sea of storage on that die.

> There is a longer term issue for how this plays out. To *me* the correct answer for everyone (from Apple to
> AMD to Intel) going forward is an IO die incorporating memory controller, and huge L4 (sans tags), with the
> logic sitting on top of that so that communication is via bumps or TSVs, high bandwidth low latency low power,
> and with L4 tags on the logic die. L4 could be SRAM, eDRAM, or MRAM depending on what tech gives the best balance
> of power vs latency vs capacity. So the primary interesting issue is how soon we get to that...
>
>
> > Honestly, 12nm is mostly just 14nm with different libraries (for density) and transistor/contact
> > optimization. I/O doesn't need logic libraries, ergo its 14nm.
> >
> > David
>
>

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            eDRAM too expensiveDavid Kanter2019/01/13 02:34 PM
              eDRAM too expensiveAdrian2019/01/13 08:51 PM
                eDRAM too expensiveAdrian2019/01/13 09:01 PM
                eDRAM too expensiveRicardo B2019/01/14 11:06 AM
                  Zen PHY speedsJeff S.2019/01/14 11:40 AM
                  eDRAM too expensiveAdrian2019/01/14 12:44 PM
                    Zen target process (was: eDRAM too expensive)hobold2019/01/14 02:42 PM
                      Zen target process (was: eDRAM too expensive)Adrian2019/01/14 09:13 PM
                        Zen target process (was: eDRAM too expensive)hobold2019/01/15 08:28 PM
                    eDRAM too expensiveRicardo B2019/01/15 03:40 AM
                    eDRAM too expensiveRicardo B2019/01/15 08:26 AM
              eDRAM too expensiveMaynard Handley2019/01/14 10:38 AM
                eDRAM too expensiveanon2019/01/14 01:00 PM
                  eDRAM too expensiveMaynard Handley2019/01/14 01:43 PM
                    eDRAM too expensiveDan Fay2019/01/14 02:16 PM
                      eDRAM too expensiveMaynard Handley2019/01/14 03:40 PM
                        eDRAM too expensiveDan Fay2019/01/14 04:58 PM
                    eDRAM too expensivesomeone2019/01/15 08:20 AM
                eDRAM too expensiveanon2019/01/14 03:34 PM
                  eDRAM too expensiveMaynard Handley2019/01/14 05:34 PM
                eDRAM too expensiveanon2019/01/15 01:06 AM
            AMD IO diejuanrga2019/01/14 03:04 AM
              AMD IO dieMaynard Handley2019/01/14 10:42 AM
                AMD IO dieAlberto2019/01/14 02:00 PM
                AMD IO diejuanrga2019/01/15 02:54 AM
                AMD IO die size & functionalityWes Felter2019/01/15 11:12 AM
                  AMD IO die size & functionalityjuanrga2019/01/15 11:43 AM
                  AMD IO die size & functionalityAlberto2019/01/15 12:57 PM
                    AMD CPU die size & functionalityWes Felter2019/01/15 04:35 PM
                      AMD CPU die size & functionalityanon2019/01/16 01:32 AM
                        AMD CPU die size & functionalityAlberto2019/01/16 05:40 AM
                      AMD CPU die size & functionalityJan Olšan2019/01/16 07:11 AM
                  AMD IO die size & functionalityMaynard Handley2019/01/16 09:17 AM
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