eDRAM too expensive

By: Ricardo B (ricardo.delete@this.xxxxx.xx), January 15, 2019 4:40 am
Room: Moderated Discussions
Adrian (a.delete@this.acm.org) on January 14, 2019 12:44 pm wrote:
> Ricardo B (ricardo.b.delete@this.xxxxx.xx) on January 14, 2019 11:06 am wrote:
> > Adrian (a.delete@this.acm.org) on January 13, 2019 8:51 pm wrote:
> > >
> > > 2. The new I/O dies also need higher speed SERDES for the other interfaces, e.g. for
> > > the inter-chip links, probably up to at least 20 Gb/s, more likely up to 25 Gb/s.
> > >
> > > Such SERDES designs were already existing and proven for the IBM process, while the original
> > > Zen 14 nm process seemed to not be able to reach serial speeds much above 10 Gb/s.
> >
> > I double GloFo 14 nm process is a limiting factor for SERDES speed.
> >
> > Here, a 28 Gbit/s SERDES implemented in TSMC 28 nm.
> > https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6894632
> >
> >
> >
> I do not have any information about the TSMC 28 nm and newer processes, because I have designed CMOS
> ICs only down to 45 nm and even then not for the TSMC processes but for IBM/Samsung processes.
> Nevertheless, I doubt that things have changed a lot during the last decade.
> This paper describes an implementation in a process that offered not only logic transistors but also
> well characterized analog transistors, bump inductors and metal-insulator-metal capacitors.
> Back when I still had access to CMOS process data, such components were not available in the
> base CMOS processes used for implementing processors or memories, but only in more expensive
> process variants intended for implementing devices with RF parts, e.g. WiFi or phone modems.
> Because of this, I doubt that the described SERDES is implemented in the
> same 28 nm process as that used e.g. for ARM processors or for GPUs.
> Nevertheless, it is possible that the continuous increase in the speed of the serial interfaces might
> have forced the availability of good analog components even in the standard logic CMOS processes.ry-leading and proven transceiver technology for each 28-nm device family performance range. Altera’s 28-nm devices support transceiver speeds from 600 Mbps to 28 Gbps.
Product architecture—On-chip memories
> Still, I find it difficult to believe this, because the IC designers have always requested such
> devices but the process designers have always been extremely reluctant to provide them.

Things haven't indeed changed much in a decade.
That said, either today or a decade ago or even more, a chip made of nothing but CMOS logic won't be of much use.

(a) Without analog components you cannot implement PLL/DLL and thus you can't perform on chip frequency synthesis.
(b) Without analog components you cannot implement PLL/DLL PLL/DLL, drivers, amplifiers, on-chip termination circuit, etc, and thus you cannot implement any but rather slow (<
> Regarding Zen, we know that the serial interfaces already consume a quite large part of the total power. Doubling
> or tripling the speed might increase the power consumption of the interfaces to unacceptable levels.
> This could be mitigated by a more clever design, but I doubt that
> the first Zen generation was very far from an optimal design.

> If they do not use the IBM process, then it is still very likely that they do not use the original
> GloFo 14 nm process but some tweaked variant, e.g. one with better passive components (inductors
> & capacitors), which were not available the first time when Zen was designed.

The IBM process is FD-SOI.
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