eDRAM too expensive

By: Ricardo B (ricardo.b.delete@this.xxxxx.xx), January 15, 2019 9:26 am
Room: Moderated Discussions
(crap, I just noticed my other post was garbled)

Adrian (a.delete@this.acm.org) on January 14, 2019 12:44 pm wrote:
> Ricardo B (ricardo.b.delete@this.xxxxx.xx) on January 14, 2019 11:06 am wrote:
> > Adrian (a.delete@this.acm.org) on January 13, 2019 8:51 pm wrote:
> > >
> > > 2. The new I/O dies also need higher speed SERDES for the other interfaces, e.g. for
> > > the inter-chip links, probably up to at least 20 Gb/s, more likely up to 25 Gb/s.
> > >
> > > Such SERDES designs were already existing and proven for the IBM process, while the original
> > > Zen 14 nm process seemed to not be able to reach serial speeds much above 10 Gb/s.
> >
> > I double GloFo 14 nm process is a limiting factor for SERDES speed.
> >
> > Here, a 28 Gbit/s SERDES implemented in TSMC 28 nm.
> > https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6894632
> >
> >
> >
> I do not have any information about the TSMC 28 nm and newer processes, because I have designed CMOS
> ICs only down to 45 nm and even then not for the TSMC processes but for IBM/Samsung processes.
> Nevertheless, I doubt that things have changed a lot during the last decade.
> This paper describes an implementation in a process that offered not only logic transistors but also
> well characterized analog transistors, bump inductors and metal-insulator-metal capacitors.
> Back when I still had access to CMOS process data, such components were not available in the
> base CMOS processes used for implementing processors or memories, but only in more expensive
> process variants intended for implementing devices with RF parts, e.g. WiFi or phone modems.
> Because of this, I doubt that the described SERDES is implemented in the
> same 28 nm process as that used e.g. for ARM processors or for GPUs.
> Nevertheless, it is possible that the continuous increase in the speed of the serial interfaces might
> have forced the availability of good analog components even in the standard logic CMOS processes.
> Still, I find it difficult to believe this, because the IC designers have always requested such
> devices but the process designers have always been extremely reluctant to provide them.

Things haven't indeed changed much in a decade.
That said, either today or a decade ago or even more, a chip made of nothing but CMOS logic won't be of much use.

(a) Without analog components you cannot implement PLL/DLL and thus you can't perform on chip frequency synthesis.
(b) Without analog components you cannot implement PLL/DLL PLL/DLL, drivers, amplifiers, on-chip termination circuit, etc, and thus you cannot implement any but rather slow (under 1 Gbit/s) digital I/O links.
(c) Without analog components you cannot implement analog filters, DAC, ADC, etc and thus you cannot have mixed signal chips such as smartphone SoC with integrated modem.

In truth, analog components have long been needed and available for CMOS digital processes.
However, the availability and access varies over process life.
In a new state of the art process, fewer options may be available, their models may be poor and only available for the foundry designers and it's close partners.
Other clients have to make do with abstract views of standard cells and other blocks provided by the foundry and partners.

As a process matures, it gains options, models improve and access becomes broader.
Though even then, in this business it's strictly on a need to know basis with rather pedantic NDAs.

BTW, some more relevant examples of high speed SERDES on CMOS processes:
- NVIDIA P100 implements 20 Gbit/s NVLINK 2.0 on TSMC 16 nm FinFET and V100 implements 25 Gbit/s NVLINK 3.0 on 12 nm FinFET.
- IBM POWER8+ implements 20 Gbit/s NVLINK 2.0 on GloFo/IBM 22 nm FD-SOI and POWER 9 implements 25 Gbit/s NVLINK 3.0 on GloFo/IBM 14 nm FD-SOI FinFET.

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                eDRAM too expensiveAdrian2019/01/13 10:01 PM
                eDRAM too expensiveRicardo B2019/01/14 12:06 PM
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                  eDRAM too expensiveAdrian2019/01/14 01:44 PM
                    Zen target process (was: eDRAM too expensive)hobold2019/01/14 03:42 PM
                      Zen target process (was: eDRAM too expensive)Adrian2019/01/14 10:13 PM
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              eDRAM too expensiveMaynard Handley2019/01/14 11:38 AM
                eDRAM too expensiveanon2019/01/14 02:00 PM
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                        eDRAM too expensiveDan Fay2019/01/14 05:58 PM
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                eDRAM too expensiveanon2019/01/14 04:34 PM
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                      AMD CPU die size & functionalityJan Olšan2019/01/16 08:11 AM
                  AMD IO die size & functionalityMaynard Handley2019/01/16 10:17 AM
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