Zen target process (was: eDRAM too expensive)

By: hobold (hobold.delete@this.vectorizer.org), January 15, 2019 9:28 pm
Room: Moderated Discussions
Adrian (a.delete@this.acm.org) on January 14, 2019 9:13 pm wrote:
> hobold (hobold.delete@this.vectorizer.org) on January 14, 2019 2:42 pm wrote:

[...]
> > In other words, Zen seeming to be wire limited at 14nm, could this be a side effect of
> > the chip being balanced for a different relation between wire delays and transistor delays?
> > More targeted at what 7nm is expected to be rather than what 14nm actually is?
> >

[...]
>
> In conclusion, I do not believe that such a strategy can be applied to
> the detailed design, e.g. to the design of a SERDES or of an ALU.
>
[...]
> Using such approximate rules, it should be possible to have a strategy of evolution of the CPU structure
> at each process generation and it should be possible indeed to choose an architecture that will
> be closer to optimal at a future process node, in order to mimimize the design effort.


Appreciate the detailed answer, thanks!
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                eDRAM too expensiveRicardo B2019/01/14 12:06 PM
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                    Zen target process (was: eDRAM too expensive)hobold2019/01/14 03:42 PM
                      Zen target process (was: eDRAM too expensive)Adrian2019/01/14 10:13 PM
                        Zen target process (was: eDRAM too expensive)hobold2019/01/15 09:28 PM
                    eDRAM too expensiveRicardo B2019/01/15 04:40 AM
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              eDRAM too expensiveMaynard Handley2019/01/14 11:38 AM
                eDRAM too expensiveanon2019/01/14 02:00 PM
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                      AMD CPU die size & functionalityJan Olšan2019/01/16 08:11 AM
                  AMD IO die size & functionalityMaynard Handley2019/01/16 10:17 AM
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