AMD CPU die size & functionality

By: Alberto (, January 16, 2019 6:40 am
Room: Moderated Discussions
anon ( on January 16, 2019 1:32 am wrote:
> Wes Felter ( on January 15, 2019 4:35 pm wrote:
> > Alberto ( on January 15, 2019 12:57 pm wrote:
> > > Wes Felter ( on January 15, 2019 11:12 am wrote:
> >
> > > > The Zeppelin (Ryzen 1xxx) die is 212 mm2 and its CCXs are 88 mm2 leaving 124 mm2 for the uncore. Now
> > > > we see that the Matisse (Ryzen 3xxx) IO die is 122 mm2 — virtually the same size on the same process
> > > > for the same functionality. I know this is highly simplistic but it makes a lot of sense.
> > > >
> > > > And if you multiply the 124 mm2 by 4 for Rome you get 500 mm2 while the Rome IO
> > > > die is smaller (there is presumably redundant stuff that can be eliminated), so
> > > > I don't see room for L4 there either, although maybe a snoop filter would be nice.
> > >
> > > So your calculations say the shift to 7nm ended in an advantage of only 8mm2 in the 8 cores chiplet
> > > (yes there is a larger L3 and the interface to the I/O chip but the new process is very compact).
> > > Strange.
> > > The implementation looks suboptimal at the best, more like a foundry 10nm to be generous.
> >
> > I don't really know what's up with the CPU chiplet. Clearly the Zen 2 cores are larger due
> > to double AVX and the L3 is larger as you said. I don't think it would make sense to move
> > uncore functionality into the CPU chiplet so I doubt that's where the area is going. Maybe
> > there's a fat SDF/GMI in the CPU chiplet and another SDF/GMI(s) in the IO die.
> >
> > The Matisse IO die is massive compared to, say, the Coffee Lake uncore but I think that's
> > fat inherited from Zeppelin. I don't think there's magic awesomeness hiding anywhere.
> >
> If the L3 doubled and scaling is ~2x then that would already cost 16 mm². The FPU on Zen was
> ~1.2 mm² iirc so assuming the same scaling and doubled size for 256 bit that's another 5 mm².
> Already less than 60 mm² left. Add the IFOP, IF between the CCX and some other minor things
> and we're well below that, meaning each core would grow significantly less than 2 mm² (so from
> 7 to less than 11 in 14nm equivalent), which seems perfectly reasonable. If the IFOP and other
> things add up to ~8 mm² Zen2 would only be around as large as Skylake in 14nm.

Or maybe the scaling is not 0.5X but 0.65/0.70X like in other shrinks of past years in high power SKUs. A larger core, a doubled L3 et voilà a not so compact piece of silicon.
Another hypothesis is the utilization of fast libraries to rise the clock speed, these are silicon hungry but they give a good clock boost. Ryzen was clock limited unfortunately with its compact libraries.
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              eDRAM too expensiveMaynard Handley2019/01/14 11:38 AM
                eDRAM too expensiveanon2019/01/14 02:00 PM
                  eDRAM too expensiveMaynard Handley2019/01/14 02:43 PM
                    eDRAM too expensiveDan Fay2019/01/14 03:16 PM
                      eDRAM too expensiveMaynard Handley2019/01/14 04:40 PM
                        eDRAM too expensiveDan Fay2019/01/14 05:58 PM
                    eDRAM too expensivesomeone2019/01/15 09:20 AM
                eDRAM too expensiveanon2019/01/14 04:34 PM
                  eDRAM too expensiveMaynard Handley2019/01/14 06:34 PM
                eDRAM too expensiveanon2019/01/15 02:06 AM
            AMD IO diejuanrga2019/01/14 04:04 AM
              AMD IO dieMaynard Handley2019/01/14 11:42 AM
                AMD IO dieAlberto2019/01/14 03:00 PM
                AMD IO diejuanrga2019/01/15 03:54 AM
                AMD IO die size & functionalityWes Felter2019/01/15 12:12 PM
                  AMD IO die size & functionalityjuanrga2019/01/15 12:43 PM
                  AMD IO die size & functionalityAlberto2019/01/15 01:57 PM
                    AMD CPU die size & functionalityWes Felter2019/01/15 05:35 PM
                      AMD CPU die size & functionalityanon2019/01/16 02:32 AM
                        AMD CPU die size & functionalityAlberto2019/01/16 06:40 AM
                      AMD CPU die size & functionalityJan Olšan2019/01/16 08:11 AM
                  AMD IO die size & functionalityMaynard Handley2019/01/16 10:17 AM
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