modern DDR4 array microphotos?

By: Jeff S. (, February 19, 2019 7:47 am
Room: Moderated Discussions
Does anybody have a good public source for area breakdown on modern (say, DDR4 and ~20nm or better) DRAM array area usage breakdown? I was curious in particular about decoder and sense amp area vs. cell array size, but not quite enough to ask Chipworks for who knows how much. All I have been able to find so far are die shots so small/zoomed out that I can't make out any array structure, or electron microscope scans zoomed in just above cell dimensions.

I'm also interested in where designs like MoSys's 1T-SRAM might sit relative to commodity large >=64 MiB DRAM array and 6T SRAM arrays on a modern node, I would appreciate hearing about it if anybody else has a clue.


(And yes I know that the commodity DRAM market is extraordinarily cut-throat and highly tuned for capacity per area above all else, etc., etc., but I'm looking for more quantitative data.)
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modern DDR4 array microphotos?Jeff S.2019/02/19 07:47 AM
  modern DDR4 array microphotos?bartoni2019/02/19 10:21 AM
    modern DDR4 array microphotos?Jeff S.2019/02/19 11:15 AM
      modern DDR4 array microphotos?Jeff S.2019/02/19 11:34 AM
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