By: Wilco (Wilco.dijkstra.delete@this.ntlworld.com), February 20, 2019 5:40 pm
Room: Moderated Discussions
dmcq (dmcq.delete@this.fano.co.uk) on February 20, 2019 4:49 pm wrote:
> Wilco (Wilco.dijkstra.delete@this.ntlworld.com) on February 20, 2019 3:45 pm wrote:
> > dmcq (dmcq.delete@this.fano.co.uk) on February 20, 2019 3:09 pm wrote:
> > > Wilco (Wilco.dijkstra.delete@this.ntlworld.com) on February 20, 2019 2:49 pm wrote:
> > > > dmcq (dmcq.delete@this.fano.co.uk) on February 20, 2019 2:16 pm wrote:
> > > > > Wilco (Wilco.dijkstra.delete@this.ntlworld.com) on February 20, 2019 1:31 pm wrote:
> > > > > > dmcq (dmcq.delete@this.fano.co.uk) on February 20, 2019 1:01 pm wrote:
> > > > > > > Michael S (already5chosen.delete@this.yahoo.com) on February 20, 2019 12:21 pm wrote:
> > > > > > > > dmcq (dmcq.delete@this.fano.co.uk) on February 20, 2019 11:49 am wrote:
> > > > > > > > > Michael S (already5chosen.delete@this.yahoo.com) on February 20, 2019 9:41 am wrote:
> > > > > > > > > > dmcq (dmcq.delete@this.fano.co.uk) on February 20, 2019 9:03 am wrote:
> > > > > > > > > > >
> > > > > > > > > > > And their ARMv8,1-M architecture
> > > > > > > > > > > for Cortex-M microcontrollers totally abandons any pretence of a RISC architecture!
> > > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > WTF are you talking about?!
> > > > > > > > >
> > > > > > > > > The stuff in this from The Register
> > > > > > > > > The Lance Arm-strong of performance-enhanced CPUs: Armv8.1-M
> > > > > > > > > arch jams vector math into super-microcontrollers
> > > > > > > > > No fuck is necessary in asking a question like that.
> > > > > > > >
> > > > > > > > It is necessary because, unlike you, I actually read introduction whitepaper
> > > > > > > > and took a brief look into draft of 8.1M reference manual. There is absolutely
> > > > > > > > nothing less RISCy than what was here since introduction of Thumb2.
> > > > > > > > It's still load-store and still only 2 variants of instruction width.
> > > > > > > > Unless you consider scatter-gather unRISCy. But than even Alpha is unRISCy, because of Tarantula proposal.
> > > > > > > > In ARM world scatter/gather is already in SVE which is optional, but standardized part of v8-A.
> > > > > > > >
> > > > > > > > If anything, new synchronization facilities in 8.1-A are less RISCy than anything found in Helium.
> > > > > > >
> > > > > > > You did not have enough evidence to assume I had not read
> > > > > > > that material and you were wrong in your assumption.
> > > > > > >
> > > > > > > Well I think of RISC as something where one has a set of
> > > > > > > registers and instructions and the instructions work
> > > > > > > cleanly to do one thing without having a load of status registers
> > > > > > > except perhaps some condition codes. ARM went
> > > > > > > a bit beyond that originally with load and store multiple
> > > > > > > instructions. And then Thumb had a conditional execution
> > > > > > > instruction that affected the next few instruction plus of course two lengths of instructions.
> > > > > > >
> > > > > > > This goes beyond that with lots more status with vector
> > > > > > > instruction beats and overlapping and more conditional
> > > > > > > control instructions and instructions to delimit loops.
> > > > > > > And it can interrupt anywhere and restart at any beat
> > > > > > > within a vector instruction. I think that all qualifies as not being what people think of as RISC.
> > > > > >
> > > > > > RISC is about the ISA, ie. load/store architecture, many
> > > > > > orthogonal registers, fast decode, simple addressing
> > > > > > modes, and instructions which are mostly single cycle.
> > > > > > This still ticks all those boxes. Having instructions
> > > > > > that affect state (such as changing rounding modes, setting flags etc) does not equal CISC. You could think
> > > > > > of the beats as a traditional vector processor, it enables
> > > > > > overlapping computations without hardware interlocks.
> > > > > > The DSP-style looping instructions enable zero-overhead loops using minimal hardware. So it's all aimed at
> > > > > > making implementations simpler and faster. How could that possibly be interpreted as a CISC ISA?
> > > > > >
> > > > > > Wilco
> > > > >
> > > > > Even if this can have complex loads and stores, has registers are overlaid in different ways, the
> > > > > decode must be a bit strange by now, the addressing is not simple in comparison to other machines,
> > > >
> > > > Adding a new extension always increases complexity, that's a given. It's all about minimizing that so
> > > > the gain is worth the cost. Tell me which Arm addressing modes are not simple? Base + offset with optional
> > > > write back or base + index * scale are not complex and standard across various RISC ISAs.
> > > >
> > > > > and the instructions are not single cycle, your criteria, you still say how could I possibly interpret
> > > > > this as a CISC ISA?
> > > >
> > > > Which instructions are not single cycle? The white paper showed how instructions are pipelined so
> > > > they do not need multiple cycles, and a dependent vector operation can start in the next cycle.
> > > >
> > > > Wilco
> > >
> > > I am not saying the additions are badly designed. I think the design is good. What I was saying
> > > is they don't fit into my idea of RISC. It seems to me that your definition of RISC is anything
> > > that is well designed and implemented, for instance that if the design and implementation
> > > is such that instructions can be overlapped then it becomes RISC. That RISC is good and CISC
> > > is bad, there's no alternatives and if something is done well it is RISC.
> >
> > I already explained what RISC means above. It's about ISA design that enables simple, fast,
> > pipelined implementations. Using implementation techniques like pipelining does not make
> > it RISC, but RISC certainly aims to maximise pipelining. There's a set of principles that
> > define RISC, I already mentioned most, the only one not mentioned so far is no microcode.
> > Arm has always been more complex than MIPS or Alpha, but so are Sparc, PA and Power.
> >
> > As far as I know, no CISC ISAs have been designed in the last decades, and RISC
> > has taken over practically every area in computing apart from the desktop.
> >
> > Wilco
>
> "I already explained what RISC means above."? You have and idea about it. I disagree with you.
I explained the accepted standard definition of RISC, there are plenty of books describing the history of RISC.
Wilco
> Wilco (Wilco.dijkstra.delete@this.ntlworld.com) on February 20, 2019 3:45 pm wrote:
> > dmcq (dmcq.delete@this.fano.co.uk) on February 20, 2019 3:09 pm wrote:
> > > Wilco (Wilco.dijkstra.delete@this.ntlworld.com) on February 20, 2019 2:49 pm wrote:
> > > > dmcq (dmcq.delete@this.fano.co.uk) on February 20, 2019 2:16 pm wrote:
> > > > > Wilco (Wilco.dijkstra.delete@this.ntlworld.com) on February 20, 2019 1:31 pm wrote:
> > > > > > dmcq (dmcq.delete@this.fano.co.uk) on February 20, 2019 1:01 pm wrote:
> > > > > > > Michael S (already5chosen.delete@this.yahoo.com) on February 20, 2019 12:21 pm wrote:
> > > > > > > > dmcq (dmcq.delete@this.fano.co.uk) on February 20, 2019 11:49 am wrote:
> > > > > > > > > Michael S (already5chosen.delete@this.yahoo.com) on February 20, 2019 9:41 am wrote:
> > > > > > > > > > dmcq (dmcq.delete@this.fano.co.uk) on February 20, 2019 9:03 am wrote:
> > > > > > > > > > >
> > > > > > > > > > > And their ARMv8,1-M architecture
> > > > > > > > > > > for Cortex-M microcontrollers totally abandons any pretence of a RISC architecture!
> > > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > WTF are you talking about?!
> > > > > > > > >
> > > > > > > > > The stuff in this from The Register
> > > > > > > > > The Lance Arm-strong of performance-enhanced CPUs: Armv8.1-M
> > > > > > > > > arch jams vector math into super-microcontrollers
> > > > > > > > > No fuck is necessary in asking a question like that.
> > > > > > > >
> > > > > > > > It is necessary because, unlike you, I actually read introduction whitepaper
> > > > > > > > and took a brief look into draft of 8.1M reference manual. There is absolutely
> > > > > > > > nothing less RISCy than what was here since introduction of Thumb2.
> > > > > > > > It's still load-store and still only 2 variants of instruction width.
> > > > > > > > Unless you consider scatter-gather unRISCy. But than even Alpha is unRISCy, because of Tarantula proposal.
> > > > > > > > In ARM world scatter/gather is already in SVE which is optional, but standardized part of v8-A.
> > > > > > > >
> > > > > > > > If anything, new synchronization facilities in 8.1-A are less RISCy than anything found in Helium.
> > > > > > >
> > > > > > > You did not have enough evidence to assume I had not read
> > > > > > > that material and you were wrong in your assumption.
> > > > > > >
> > > > > > > Well I think of RISC as something where one has a set of
> > > > > > > registers and instructions and the instructions work
> > > > > > > cleanly to do one thing without having a load of status registers
> > > > > > > except perhaps some condition codes. ARM went
> > > > > > > a bit beyond that originally with load and store multiple
> > > > > > > instructions. And then Thumb had a conditional execution
> > > > > > > instruction that affected the next few instruction plus of course two lengths of instructions.
> > > > > > >
> > > > > > > This goes beyond that with lots more status with vector
> > > > > > > instruction beats and overlapping and more conditional
> > > > > > > control instructions and instructions to delimit loops.
> > > > > > > And it can interrupt anywhere and restart at any beat
> > > > > > > within a vector instruction. I think that all qualifies as not being what people think of as RISC.
> > > > > >
> > > > > > RISC is about the ISA, ie. load/store architecture, many
> > > > > > orthogonal registers, fast decode, simple addressing
> > > > > > modes, and instructions which are mostly single cycle.
> > > > > > This still ticks all those boxes. Having instructions
> > > > > > that affect state (such as changing rounding modes, setting flags etc) does not equal CISC. You could think
> > > > > > of the beats as a traditional vector processor, it enables
> > > > > > overlapping computations without hardware interlocks.
> > > > > > The DSP-style looping instructions enable zero-overhead loops using minimal hardware. So it's all aimed at
> > > > > > making implementations simpler and faster. How could that possibly be interpreted as a CISC ISA?
> > > > > >
> > > > > > Wilco
> > > > >
> > > > > Even if this can have complex loads and stores, has registers are overlaid in different ways, the
> > > > > decode must be a bit strange by now, the addressing is not simple in comparison to other machines,
> > > >
> > > > Adding a new extension always increases complexity, that's a given. It's all about minimizing that so
> > > > the gain is worth the cost. Tell me which Arm addressing modes are not simple? Base + offset with optional
> > > > write back or base + index * scale are not complex and standard across various RISC ISAs.
> > > >
> > > > > and the instructions are not single cycle, your criteria, you still say how could I possibly interpret
> > > > > this as a CISC ISA?
> > > >
> > > > Which instructions are not single cycle? The white paper showed how instructions are pipelined so
> > > > they do not need multiple cycles, and a dependent vector operation can start in the next cycle.
> > > >
> > > > Wilco
> > >
> > > I am not saying the additions are badly designed. I think the design is good. What I was saying
> > > is they don't fit into my idea of RISC. It seems to me that your definition of RISC is anything
> > > that is well designed and implemented, for instance that if the design and implementation
> > > is such that instructions can be overlapped then it becomes RISC. That RISC is good and CISC
> > > is bad, there's no alternatives and if something is done well it is RISC.
> >
> > I already explained what RISC means above. It's about ISA design that enables simple, fast,
> > pipelined implementations. Using implementation techniques like pipelining does not make
> > it RISC, but RISC certainly aims to maximise pipelining. There's a set of principles that
> > define RISC, I already mentioned most, the only one not mentioned so far is no microcode.
> > Arm has always been more complex than MIPS or Alpha, but so are Sparc, PA and Power.
> >
> > As far as I know, no CISC ISAs have been designed in the last decades, and RISC
> > has taken over practically every area in computing apart from the desktop.
> >
> > Wilco
>
> "I already explained what RISC means above."? You have and idea about it. I disagree with you.
I explained the accepted standard definition of RISC, there are plenty of books describing the history of RISC.
Wilco
Topic | Posted By | Date |
---|---|---|
ARM announces Ares | nobody in particular | 2019/02/20 07:35 AM |
ARM announces Ares | Adrian | 2019/02/20 07:39 AM |
ARM announces Ares | dmcq | 2019/02/20 09:03 AM |
ARM announces Ares | Michael S | 2019/02/20 09:41 AM |
ARM announces Ares | dmcq | 2019/02/20 11:49 AM |
ARM announces Ares | Michael S | 2019/02/20 12:21 PM |
ARM announces Ares | dmcq | 2019/02/20 01:01 PM |
ARM announces Ares | Wilco | 2019/02/20 01:31 PM |
ARM announces Ares | dmcq | 2019/02/20 02:16 PM |
ARM announces Ares | Wilco | 2019/02/20 02:49 PM |
ARM announces Ares | dmcq | 2019/02/20 03:09 PM |
ARM announces Ares | Wilco | 2019/02/20 03:45 PM |
ARM announces Ares | nobody in particular | 2019/02/20 03:55 PM |
ARM announces Ares | Dan Fay | 2019/02/20 04:44 PM |
ARM announces Ares | Wilco | 2019/02/20 06:06 PM |
ARM announces Ares | Dan Fay | 2019/02/21 07:27 AM |
ARM announces Ares | dmcq | 2019/02/20 04:49 PM |
ARM announces Ares | Wilco | 2019/02/20 05:40 PM |
ARM announces Ares | Charles | 2019/02/21 01:16 AM |
ARM announces Ares | Michael S | 2019/02/21 01:26 AM |
ARM announces Ares | anon | 2019/02/20 07:55 PM |
ARM announces Ares | JS | 2019/02/20 11:59 PM |
*has not hasn't (NT) | JS | 2019/02/21 12:01 AM |
ARM announces Ares | Salvatore De Dominicis | 2019/02/21 06:05 AM |
Definitions of RISC | Brendan | 2019/02/21 09:07 AM |
Definitions of RISC | Michael S | 2019/02/21 09:16 AM |
PDP-8 Not Usually Considered RISC | Mark Roulo | 2019/02/21 01:10 PM |
PDP-8 Not Usually Considered RISC | rwessel | 2019/02/21 06:13 PM |
Definitions of RISC | Adrian | 2019/02/21 01:42 PM |
Definitions of RISC (nod to John Mashey and comp.arch) | wumpus | 2019/02/21 05:29 PM |
Definitions of RISC (nod to John Mashey and comp.arch) | none | 2019/02/21 11:32 PM |
Definitions of RISC (nod to John Mashey and comp.arch) | Michael S | 2019/02/22 03:28 AM |
Definitions of RISC (nod to John Mashey and comp.arch) | none | 2019/02/22 07:01 AM |
ARM announces Ares | lockederboss | 2019/02/20 08:56 AM |
stability? (NT) | anonymous2 | 2019/02/20 09:01 AM |
ARM announces Ares | dmcq | 2019/02/20 09:05 AM |
ARM announces Ares | Groo | 2019/02/20 09:11 AM |
ARM announces Ares | Andrei Frumusanu | 2019/02/20 10:49 AM |
ARM announces Ares | Linus Torvalds | 2019/02/20 09:36 AM |
ARM announces Ares | Michael S | 2019/02/20 09:54 AM |
ARM announces Ares | Geoff Langdale | 2019/02/20 02:07 PM |
ARM announces Ares | dmcq | 2019/02/20 02:32 PM |
ARM announces Ares | none | 2019/02/20 11:03 PM |
That last line should have been removed :-) (NT) | none | 2019/02/20 11:04 PM |
ARM announces Ares | Michael S | 2019/02/21 12:47 AM |
ARM announces Ares | none | 2019/02/21 02:59 AM |
ARM announces Ares | Michael S | 2019/02/21 03:45 AM |
ARM announces Ares | dmcq | 2019/02/21 04:18 AM |
ARM announces Ares | Simon Farnsworth | 2019/02/22 08:43 AM |
ARM announces Ares | anon | 2019/02/20 08:27 PM |
ARM announces Ares | Michael S | 2019/02/21 12:53 AM |
ARM announces Ares | Linus Torvalds | 2019/02/21 08:03 AM |
ARM announces Ares | Michael S | 2019/02/21 08:35 AM |
ARM announces Ares | Michael S | 2019/02/21 08:51 AM |
ARM announces Ares | Foo_ | 2019/02/21 01:40 PM |
ARM announces Ares | aaron spink | 2019/02/21 02:56 PM |
ARM announces Ares | Linus Torvalds | 2019/02/21 03:27 PM |
ARM announces Ares | Stoffels | 2019/02/21 11:21 PM |
ARM announces Ares | Michael S | 2019/02/22 03:15 AM |
ARM announces Ares | Simon Farnsworth | 2019/02/22 08:41 AM |
ARM announces Ares | none | 2019/02/22 09:30 AM |
In other words: nobody will ever get fired for choosing x86 (NT) | Gabriele Svelto | 2019/02/24 12:32 PM |
In other words: nobody will ever get fired for choosing x86 | Simon Farnsworth | 2019/02/25 03:53 AM |
ARM announces Ares | Foo_ | 2019/02/22 01:52 AM |
ARM announces Ares | Gabriele Svelto | 2019/02/24 12:31 PM |
ARM announces Ares | Maynard Handley | 2019/02/25 02:57 AM |
ARM announces Ares | Gabriele Svelto | 2019/02/25 03:21 AM |
ARM announces Ares | Michael S | 2019/02/25 03:58 AM |
ARM announces Ares | nobody in particular | 2019/02/25 04:21 AM |
ARM announces Ares | Adrian | 2019/02/26 07:02 AM |
ARM announces Ares | Maynard Handley | 2019/02/25 11:32 PM |
ARM announces Ares | Gabriele Svelto | 2019/02/26 11:14 AM |
ARM announces Ares | David Hess | 2019/03/19 04:34 PM |
ARM announces Ares | none | 2019/02/26 12:34 AM |
ARM announces Ares | Gabriele Svelto | 2019/02/26 11:16 AM |
ARM announces Ares | none | 2019/02/26 11:19 PM |
ARM announces Ares | end of an era | 2019/02/24 02:18 PM |
Word salad bot strikes again (NT) | nanon | 2019/02/24 11:26 PM |
ARM announces Ares | hobel | 2019/02/25 01:10 AM |
ARM announces Ares | Michael S | 2019/02/25 01:52 AM |
ARM announces Ares | hobel | 2019/02/25 09:48 AM |
ARM announces Ares | Andrew Clough | 2019/02/25 01:07 PM |
ARM announces Ares | Maynard Handley | 2019/02/25 11:38 PM |
ARM announces Ares | John Yates | 2019/02/26 02:43 PM |
ARM announces Ares | Howard Chu | 2019/02/27 05:55 AM |
ARM announces Ares | David Hess | 2019/03/19 04:22 PM |
ARM announces Ares | David Hess | 2019/03/19 03:54 PM |
ARMY announces Ares | dmcq | 2019/03/20 02:12 AM |
ARMY announces Ares | David Hess | 2019/03/20 04:47 AM |
ARMY announces Ares | dmcq | 2019/03/20 05:05 AM |
ARM announces Ares | Groo | 2019/02/21 09:23 AM |
ARM announces Ares | Michael S | 2019/02/21 09:29 AM |
ARM announces Ares | David Hess | 2019/03/19 04:44 PM |
ARM announces Ares | juanrga | 2019/02/21 10:52 AM |
ARM announces Ares | anon | 2019/02/21 07:19 PM |
ARM announces Ares | hobel | 2019/02/22 02:40 AM |
software ecosystems | RichardC | 2019/02/21 03:31 PM |
software ecosystems | Foo_ | 2019/02/22 02:15 AM |
ARM announces Ares | dmcq | 2019/02/21 04:31 PM |
+ on hyperscaling | dmcq | 2019/02/22 07:23 AM |
+ on hyperscaling | Maynard Handley | 2019/02/22 07:38 AM |
+ on hyperscaling | juanrga | 2019/02/22 10:57 AM |
+ on hyperscaling | dmcq | 2019/02/22 07:23 AM |
sorry duplicate | dmcq | 2019/02/22 07:26 AM |
ARM announces Ares | anon | 2019/02/21 07:34 PM |
ARM announces Ares | Brett | 2019/02/21 09:20 PM |
ARM announces Ares | A. Wilcox | 2019/02/22 02:52 PM |
ARM announces Ares | Doug S | 2019/02/20 02:30 PM |
ARM announces Ares | dmcq | 2019/02/20 03:14 PM |
ARM announces Ares | Doug S | 2019/02/21 07:40 AM |
ARM announces Ares | aaron spink | 2019/02/21 03:05 PM |
ARM announces Ares | Maynard Handley | 2019/02/22 07:48 AM |
ARM announces Ares | juanrga | 2019/02/21 01:28 AM |
ARM announces Ares | Michael S | 2019/02/21 02:25 AM |
ARM announces Ares | juanrga | 2019/02/22 03:09 AM |
ARM announces Ares | Maynard Handley | 2019/02/22 07:51 AM |
ARM announces Ares | David Soul | 2019/02/22 10:47 AM |
ARM announces Ares | juanrga | 2019/02/22 11:23 AM |
Chicken or egg, both. | Brett | 2019/02/22 01:21 PM |
Chicken or egg, both. | David Soul | 2019/02/22 05:05 PM |
Chicken or egg, both. | Brett | 2019/02/22 08:55 PM |
ARM sales | juanrga | 2019/02/23 02:55 AM |
ARM sales | aaron spink | 2019/02/23 07:47 AM |
Chicken or egg, both. | Ronald Maas | 2019/02/23 05:33 PM |
Chicken or egg, both. | Magagop | 2019/02/24 10:18 PM |
why not? (NT) | Michael S | 2019/02/25 01:03 AM |
why not? | Not the parent | 2019/02/25 09:36 AM |
why not? | Michael S | 2019/02/25 09:43 AM |
why not? | dmcq | 2019/02/25 10:35 AM |
why not? | Michael S | 2019/02/25 11:03 AM |
why not? | dmcq | 2019/02/25 11:29 AM |
why not? | Not the parent | 2019/02/26 09:08 AM |
why not? | Doug S | 2019/02/26 11:05 AM |
why not? | Not the parent | 2019/02/27 03:51 AM |
why not? | Doug S | 2019/02/27 11:15 AM |
why not? | Not the parent | 2019/02/28 12:43 AM |
why not? | anon | 2019/02/26 10:22 PM |
why not? | Not the parent | 2019/02/27 03:59 AM |
why not? | anon | 2019/02/27 05:42 AM |
why not? | Magagop | 2019/02/27 02:31 PM |
why not? | anon | 2019/02/27 04:02 PM |
why not? | dmcq | 2019/02/27 04:25 PM |
why not? | anon | 2019/02/27 04:56 PM |
why not? | dmcq | 2019/02/27 05:19 PM |
why not? | anon | 2019/02/27 05:46 PM |
why not? | Wilco | 2019/02/28 04:49 AM |
why not? | Jukka Larja | 2019/02/28 06:02 AM |
why not? | Michael S | 2019/02/28 07:32 AM |
why not? | Wilco | 2019/02/28 08:40 AM |
why not? | Doug S | 2019/02/28 09:13 AM |
why not? | Foo_ | 2019/03/01 06:35 AM |
why not? | Doug S | 2019/03/01 10:05 AM |
why not? | anon | 2019/03/01 01:32 PM |
why not? | dmcq | 2019/03/01 02:13 PM |
why not? | anon | 2019/03/01 03:13 PM |
why not? | dmcq | 2019/03/02 02:56 AM |
why not? | anon | 2019/03/02 09:09 AM |
why not? | dmcq | 2019/03/02 09:41 AM |
why not? | anon | 2019/03/02 11:19 AM |
why not? | dmcq | 2019/03/03 02:48 AM |
why not? | Doug S | 2019/03/02 03:53 PM |
why not? | Michael S | 2019/03/02 04:06 PM |
why not? | Doug S | 2019/03/02 11:54 PM |
why not? | Michael S | 2019/03/03 01:58 AM |
why not? | anon | 2019/03/03 04:35 AM |
why not? | dmcq | 2019/03/03 05:33 AM |
I considired dry humor a Brittish specialty. It seems, I was wrong about it. (NT) | Michael S | 2019/03/03 05:39 AM |
why not? | anon | 2019/03/03 09:13 AM |
why not? | Michael S | 2019/03/03 11:41 AM |
why not? | dmcq | 2019/03/03 12:21 PM |
why not? | anon | 2019/03/03 03:15 PM |
why not? | anon | 2019/02/28 07:38 PM |
why not? | Not the parent | 2019/02/28 12:48 AM |
strawman (NT) | anon | 2019/02/28 07:31 PM |
why not? | Michael S | 2019/02/27 02:53 AM |
why not? | Not the parent | 2019/02/27 04:26 AM |
why not? | Michael S | 2019/02/27 04:42 AM |
why not? | dmcq | 2019/02/27 04:49 AM |
why not? | Michael S | 2019/02/27 05:21 AM |
why not? | dmcq | 2019/02/27 06:15 AM |
Selling at multiple layers | Paul A. Clayton | 2019/02/27 10:25 AM |
Selling at multiple layers | Doug S | 2019/02/27 11:45 AM |
Selling at multiple layers | Paul A. Clayton | 2019/02/27 01:32 PM |
Selling at multiple layers | Doug S | 2019/02/27 03:04 PM |
Paul A. Clayton | 2019/02/27 06:06 PM | |
Arm reference board? | Simon Farnsworth | 2019/02/28 11:34 AM |
why not? | Doug S | 2019/02/27 11:46 AM |
why not? (NT) | la mama de murgay | 2019/02/25 09:22 PM |
Chicken or egg, both. | Ronald Maas | 2019/02/25 12:23 PM |
ARM announces Ares | Gabriele Svelto | 2019/02/24 02:07 PM |
ARM announces Ares | juanrga | 2019/03/02 04:40 AM |
ARM announces Ares | Gabriele Svelto | 2019/03/02 07:08 AM |
ARM announces Ares | dmcq | 2019/03/02 09:10 AM |
ARM announces Ares | hobel | 2019/02/22 03:33 PM |
ARM announces Ares | David Soul | 2019/02/22 05:20 PM |
Troll | Doug S | 2019/02/23 12:37 AM |
Troll | David Soul | 2019/02/23 07:59 AM |
ARM announces Ares | Ennis | 2019/02/23 01:18 AM |
ARM announces Ares | Foo_ | 2019/02/23 01:38 AM |
ARM announces Ares | anon | 2019/02/23 02:46 AM |
ARM announces Ares | dmcq | 2019/02/23 04:41 AM |
ARM announces Ares | nobody in particular | 2019/02/26 02:58 AM |
expensive | anonymous2 | 2019/02/26 11:46 PM |
ARM announces Ares | Howard Chu | 2019/02/27 06:19 AM |
ARM announces Ares | Howard Chu | 2019/02/27 06:21 AM |
ARM announces Ares | dmcq | 2019/02/27 06:57 AM |
ARM announces Ares | Jukka Larja | 2019/02/27 07:11 AM |
ARM announces Ares | Michael S | 2019/02/27 07:16 AM |
ARM announces Ares | Doug S | 2019/02/27 11:49 AM |
ARM announces Ares | Michael S | 2019/02/27 12:43 PM |
ARM announces Ares | Doug S | 2019/02/27 03:06 PM |
ARM announces Ares | Gian-Carlo Pascutto | 2019/02/28 04:00 AM |
ARM announces Ares | Gian-Carlo Pascutto | 2019/02/28 04:02 AM |
ARM announces Ares | Michael S | 2019/03/01 02:47 AM |
death by a thousand cuts | Michael S | 2019/03/01 06:27 AM |
death by a thousand cuts | Foo_ | 2019/03/01 06:37 AM |
death by a thousand cuts | dmcq | 2019/03/01 11:10 AM |
ARM announces Ares | Jukka Larja | 2019/02/28 05:31 AM |
ARM announces Ares | Howard Chu | 2019/02/28 08:17 AM |
ARM announces Ares | Gabriele Svelto | 2019/02/28 02:02 PM |
ARM announces Ares | aaron spink | 2019/03/01 12:19 AM |
ARM announces Ares | Andrew Clough | 2019/02/28 10:32 AM |
ARM announces Ares | Andrew Clough | 2019/02/28 10:33 AM |
ARM announces Ares | Foo_ | 2019/03/01 12:55 AM |
ARM announces Ares | Jukka Larja | 2019/03/01 04:40 AM |
ARM announces Ares | Howard Chu | 2019/02/27 07:45 AM |
ARM announces Ares | dmcq | 2019/02/27 08:17 AM |
ARM announces Ares | dmcq | 2019/02/27 08:21 AM |
ARM announces Ares | Howard Chu | 2019/02/27 03:03 PM |
ARM announces Ares | Jukka Larja | 2019/02/28 05:03 AM |
ARM announces Ares | none | 2019/02/27 10:49 PM |
ARM announces Ares | Howard Chu | 2019/02/28 03:26 AM |
ARM announces Ares | Peter E. Fry | 2019/02/28 06:31 PM |
ARM announces Ares | Adrian | 2019/02/28 09:09 PM |
ARM announces Ares | Gabriele Svelto | 2019/03/01 11:56 PM |
ARM announces Ares | Howard Chu | 2019/03/02 09:05 AM |
ARM announces Ares | Gabriele Svelto | 2019/03/02 01:31 PM |