Adrian (a.delete@this.acm.org) on February 21, 2019 1:42 pm wrote:
> Brendan (btrotter.delete@this.gmail.com) on February 21, 2019 9:07 am wrote:
> >
> > My definition of RISC is that there's a reduced number of instructions (not a buttload
John Mashey had a long-winded explanation that he regularly posted on comp.arch, here's a link to one from 1995: https://www.yarchive.net/comp/risc_definition.html

From other posts, I think addressing modes was the most critical, but ARM breaks the RISC rules in a few other places.
3a: Thumb allows two different sizes of instruction length
3b: the main one (for thumb) is 16bit
6a: they have less than 32 integer registers
6b: architectural definition of floating point (and thus number of fp registers) is often implementation specific...

I'm not familiar enough with ARM to know the rest off the top of my head, but further down the post ARM's addressing modes are in a chart and they appear to fall in the no-man's-land between RISC and CISC (ARM doesn't have indirect addressing, but does require some complicated addressing that shouldn't require an additional memory access).

I will admit that this list doesn't appear to check for special purpose registers, something of a CISC hallmark and shunned by RISC, and feels related to the complaints against this new ARM architecture.

I think the real rule for a RISC architecture is "anything designed after the mid/late 1980s", with a possible "post-RISC" title claimed by anyone with enough ambition to break free of RISC's rules (so far, no post-RISC architecture has succeeded for general purpose computing).