none (none.delete@this.none.com) on February 21, 2019 11:32 pm wrote:
> wumpus (lost.delete@this.in.a.cave) on February 21, 2019 5:29 pm wrote:
> > Adrian (a.delete@this.acm.org) on February 21, 2019 1:42 pm wrote:
> > > Brendan (btrotter.delete@this.gmail.com) on February 21, 2019 9:07 am wrote:
> > > >
> > > > My definition of RISC is that there's a reduced number of instructions (not a buttload
> > John Mashey had a long-winded explanation that he regularly posted on comp.arch, here's
> > a link to one from 1995: https://www.yarchive.net/comp/risc_definition.html
>
> So many memories :-)
>
> > From other posts, I think addressing modes was the most critical,
> > but ARM breaks the RISC rules in a few other places.
>
> AArch64 has pre/post increment. The rest is pretty basic (col 1-7), though it can be
> argued that anything that uses 2 registers for addressing mode puts pressure on
> micro-architecture design.
>
> > 3a: Thumb allows two different sizes of instruction length
> > 3b: the main one (for thumb) is 16bit
>
> AArch64 has a single instruction length.
>
> > 6a: they have less than 32 integer registers
>
> AArch64 has 32 integer registers.
>
> > 6b: architectural definition of floating point (and thus number
> > of fp registers) is often implementation specific...
>
> AArch64 has 32 FP registers.
>
> > I'm not familiar enough with ARM to know the rest off the top of my head, but further
> > down the post ARM's addressing modes are in a chart and they appear to fall in the no-man's-land
> > between RISC and CISC (ARM doesn't have indirect addressing, but does require some complicated
> > addressing that shouldn't require an additional memory access).
>
> AArch64 is "more RISCy" than 32-bit ARM.
>
> On the other hand you forgot that ARM violates 5a: it supports unaligned accesses. But
> that's a very needed feature IMHO.
>
> > I will admit that this list doesn't appear to check for special purpose registers, something of a CISC
> > hallmark and shunned by RISC, and feels related to the complaints against this new ARM architecture.
>
> Yes on the system side ARM has become quite complex.
>

This subthread started with discussion of new additions to ARMv8-M. aarch64 is sort of offtopic, as weired as it sounds with header mentioning Ares.